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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AS4PR04MB9338.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 084bbf6a-24b2-4e9a-7c52-08df1ea4a304 X-MS-Exchange-CrossTenant-originalarrivaltime: 30 Sep 2026 03:40:56.7949 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: +Temrx0LSt0vINPRIqRAbb+nsbzfMCEvPHyMeX8LElkm7PMmXW+JwvR1eEeh3hs1kPqXIAYhKfL/B4SZ+Nc1EQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR04MB9141 Sorry, this email was missed because it did not match the filtering rules I= set. Hi Valdimir and Claudiu, Please take a look at this patch, it may affect LS1028A and S32N7 platforms= . > The current eMDIO MDC rate is 558 kHz on i.MX95 B0. This is very low, The system clock of i.MX95 NETC is 333MHz, AFAIU, the MDC rate should be 333/(2*258+1) =3D 644KHz. I'm confused that why you said the rate is 558KHz= . > but also very compatible. However, for example NXP TJA1120 PHY needs > at minimum 1 MHz MDC clock and 558 kHz does not work with that PHY. We previously used the TJA1120-SDBR daughter card to connect to the ENETC interface (RGMII) of the i.MX95 19x19 EVK board. However, we did not encoun= ter any issues with MDIO access. Furthermore, I did not see a minimum MDC frequency rate of 1MHz on the TJA1120 datasheet. I'm not sure if this is an= errata of TJA1120. >=20 > As a minimum change, increase the MDC clock to 2.5 MHz which matches The prerequisite is that NETC system clock is 333MHz, so that you can get a MDC clock rate of 2.5MHz (333/(2*66 + 1)). But unfortunately, not all NETC versions have a 333MHz system clock. For example, LS1028A is 400MHz, so the MDC rate will be 3MHz, which will be a problem. > the 802.3 specification. Also, even old PHYs like LAN8210Ai, KSZ8794, > DP83822 support up to 2.5 MHz MDC clock frequency, and it covers the > NXP TJA1120 as well. There is no known rationale for why the 558 kHz > was picked when the eMDIO driver was added. >=20 > Signed-off-by: Marek Vasut > --- > Cc: "David S. Miller" > Cc: Andrew Lunn > Cc: Clark Wang > Cc: Claudiu Manoil > Cc: Eric Dumazet > Cc: Jakub Kicinski > Cc: Paolo Abeni > Cc: Vladimir Oltean > Cc: Wei Fang > Cc: imx@lists.linux.dev > Cc: linux-kernel@vger.kernel.org > Cc: netdev@vger.kernel.org > --- > V2: Use 2.5 MHz per 802.3 spec, update commit message > --- > drivers/net/ethernet/freescale/enetc/enetc_mdio.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >=20 > diff --git a/drivers/net/ethernet/freescale/enetc/enetc_mdio.c > b/drivers/net/ethernet/freescale/enetc/enetc_mdio.c > index 998aaa394e9c4..a90a04a47befd 100644 > --- a/drivers/net/ethernet/freescale/enetc/enetc_mdio.c > +++ b/drivers/net/ethernet/freescale/enetc/enetc_mdio.c > @@ -24,7 +24,7 @@ >=20 > #define ENETC_EMDIO_CFG \ > (MDIO_CFG_HOLD(2) | \ > - MDIO_CFG_CLKDIV(258) | \ > + MDIO_CFG_CLKDIV(66) | \ > MDIO_CFG_NEG) >=20 > #define MDIO_CTL_DEV_ADDR(x) ((x) & 0x1f) > -- > 2.53.0