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charset=utf-8 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3774.500.171.1.1\)) Subject: Re: [PATCH V2 5/9] tools/perf: Update parameters for reg extract functions to use raw instruction on powerpc From: Athira Rajeev In-Reply-To: Date: Wed, 22 May 2024 19:36:38 +0530 Cc: "acme@kernel.org" , "jolsa@kernel.org" , "adrian.hunter@intel.com" , "irogers@google.com" , "namhyung@kernel.org" , "segher@kernel.crashing.org" , "linux-perf-users@vger.kernel.org" , "linuxppc-dev@lists.ozlabs.org" , "maddy@linux.ibm.com" , "kjain@linux.ibm.com" , "disgoel@linux.vnet.ibm.com" , "linux-kernel@vger.kernel.org" , "akanksha@linux.ibm.com" Content-Transfer-Encoding: quoted-printable Message-Id: References: <20240506121906.76639-1-atrajeev@linux.vnet.ibm.com> <20240506121906.76639-6-atrajeev@linux.vnet.ibm.com> To: Christophe Leroy X-Mailer: Apple Mail (2.3774.500.171.1.1) X-TM-AS-GCONF: 00 X-Proofpoint-GUID: pxPfNU_L5_ulcuL4UQvKZoCSzc05XEzC X-Proofpoint-ORIG-GUID: ujt3SqiMH9AucnqY7P2pA9e5VgKNorvw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.12.28.16 definitions=2024-05-22_07,2024-05-22_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 mlxscore=0 mlxlogscore=999 phishscore=0 suspectscore=0 adultscore=0 priorityscore=1501 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405220094 > On 7 May 2024, at 3:18=E2=80=AFPM, Christophe Leroy = wrote: >=20 >=20 >=20 > Le 06/05/2024 =C3=A0 14:19, Athira Rajeev a =C3=A9crit : >> Use the raw instruction code and macros to identify memory = instructions, >> extract register fields and also offset. The implementation addresses >> the D-form, X-form, DS-form instructions. Two main functions are = added. >> New parse function "load_store__parse" as instruction ops parser for >> memory instructions. Unlink other parser (like mov__parse), this = parser >> fills in only the "raw" field for source/target and new added = "mem_ref" >> field. This is because, here there is no need to parse the = disassembled >> code and arch specific macros will take care of extracting offset and >> regs which is easier and will be precise. >>=20 >> In powerpc, all instructions with a primary opcode from 32 to 63 >> are memory instructions. Update "ins__find" function to have "opcode" >> also as a parameter. Don't use the "extract_reg_offset", instead use >> newly added function "get_arch_regs" which will set these fields: = reg1, >> reg2, offset depending of where it is source or target ops. >=20 > Yes all instructions with a primary opcode from 32 to 63 are memory=20 > instructions, but not all memory instructions have opcode 32 to 63. >=20 >>=20 >> Signed-off-by: Athira Rajeev >> --- >> tools/perf/arch/powerpc/util/dwarf-regs.c | 33 +++++++++++++ >> tools/perf/util/annotate.c | 22 ++++++++- >> tools/perf/util/disasm.c | 59 = +++++++++++++++++++++-- >> tools/perf/util/disasm.h | 4 +- >> tools/perf/util/include/dwarf-regs.h | 4 +- >> 5 files changed, 114 insertions(+), 8 deletions(-) >>=20 >> diff --git a/tools/perf/arch/powerpc/util/dwarf-regs.c = b/tools/perf/arch/powerpc/util/dwarf-regs.c >> index e60a71fd846e..3121c70dc0d3 100644 >> --- a/tools/perf/arch/powerpc/util/dwarf-regs.c >> +++ b/tools/perf/arch/powerpc/util/dwarf-regs.c >> @@ -102,6 +102,9 @@ int regs_query_register_offset(const char *name) >> #define PPC_OP(op) (((op) >> 26) & 0x3F) >> #define PPC_RA(a) (((a) >> 16) & 0x1f) >> #define PPC_RT(t) (((t) >> 21) & 0x1f) >> +#define PPC_RB(b) (((b) >> 11) & 0x1f) >> +#define PPC_D(D) ((D) & 0xfffe) >> +#define PPC_DS(DS) ((DS) & 0xfffc) >>=20 >> int get_opcode_insn(unsigned int raw_insn) >> { >> @@ -117,3 +120,33 @@ int get_target_reg(unsigned int raw_insn) >> { >> return PPC_RT(raw_insn); >> } >> + >> +int get_offset_opcode(int raw_insn __maybe_unused) >> +{ >> + int opcode =3D PPC_OP(raw_insn); >> + >> + /* DS- form */ >> + if ((opcode =3D=3D 58) || (opcode =3D=3D 62)) >=20 > Can you re-use macros from arch/powerpc/include/asm/ppc-opcode.h ? >=20 > #define OP_LD 58 > #define OP_STD 62 Hi Christophe Sure, I will make these changes >=20 >=20 >> + return PPC_DS(raw_insn); >> + else >> + return PPC_D(raw_insn); >> +} >> + >> +/* >> + * Fills the required fields for op_loc depending on if it >> + * is a source of target. >> + * D form: ins RT,D(RA) -> src_reg1 =3D RA, offset =3D D, dst_reg1 =3D= RT >> + * DS form: ins RT,DS(RA) -> src_reg1 =3D RA, offset =3D DS, = dst_reg1 =3D RT >> + * X form: ins RT,RA,RB -> src_reg1 =3D RA, src_reg2 =3D RB, = dst_reg1 =3D RT >> + */ >> +void get_arch_regs(int raw_insn __maybe_unused, int is_source = __maybe_unused, struct annotated_op_loc *op_loc __maybe_unused) >> +{ >> + if (is_source) >> + op_loc->reg1 =3D get_source_reg(raw_insn); >> + else >> + op_loc->reg1 =3D get_target_reg(raw_insn); >> + if (op_loc->multi_regs) >> + op_loc->reg2 =3D PPC_RB(raw_insn); >> + if (op_loc->mem_ref) >> + op_loc->offset =3D get_offset_opcode(raw_insn); >> +} >=20 >> diff --git a/tools/perf/util/disasm.c b/tools/perf/util/disasm.c >> index 85692f73e78f..f41a0fadeab4 100644 >> --- a/tools/perf/util/disasm.c >> +++ b/tools/perf/util/disasm.c >> @@ -760,11 +800,20 @@ static void ins__sort(struct arch *arch) >> qsort(arch->instructions, nmemb, sizeof(struct ins), ins__cmp); >> } >>=20 >> -static struct ins_ops *__ins__find(struct arch *arch, const char = *name) >> +static struct ins_ops *__ins__find(struct arch *arch, const char = *name, int opcode) >> { >> struct ins *ins; >> const int nmemb =3D arch->nr_instructions; >>=20 >> + if (arch__is(arch, "powerpc")) { >> + /* >> + * Instructions with a primary opcode from 32 to 63 >> + * are memory instructions in powerpc. >> + */ >> + if ((opcode >=3D 31) && (opcode <=3D 63)) >=20 > Could just be if ((opcode & 0x20)) I guess. Ok,,=20 >=20 > By the way your test is wrong because opcode 31 is not only memory=20 > instructions, see example below (not exhaustive): >=20 > #define OP_31_XOP_TRAP 4 =3D=3D> No > #define OP_31_XOP_LDX 21 =3D=3D> Yes > #define OP_31_XOP_LWZX 23 =3D=3D> Yes > #define OP_31_XOP_LDUX 53 =3D=3D> Yes > #define OP_31_XOP_DCBST 54 =3D=3D> No > #define OP_31_XOP_LWZUX 55 =3D=3D> Yes > #define OP_31_XOP_TRAP_64 68 =3D=3D> No > #define OP_31_XOP_DCBF 86 =3D=3D> No > #define OP_31_XOP_LBZX 87 =3D=3D> Yes > #define OP_31_XOP_STDX 149 =3D=3D> Yes > #define OP_31_XOP_STWX 151 =3D=3D> Yes Thanks for pointing this. I checked through others in this list in = arch/powerpc/include/asm/ppc-opcode.h=20 I will have these filtered in V3 Thanks Athira >=20 >=20 >=20 >=20 >> + return &load_store_ops; >> + } >> + >> if (!arch->sorted_instructions) { >> ins__sort(arch); >> arch->sorted_instructions =3D true;