From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752894AbdHDN0g (ORCPT ); Fri, 4 Aug 2017 09:26:36 -0400 Received: from mail-pg0-f67.google.com ([74.125.83.67]:35710 "EHLO mail-pg0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752832AbdHDN0e (ORCPT ); Fri, 4 Aug 2017 09:26:34 -0400 Content-Type: text/plain; charset=euc-kr Mime-Version: 1.0 (1.0) Subject: Re: [PATCH] arm:lpae: build TTB control register value from scratch in v7_ttb_setup From: Hoeun Ryu X-Mailer: iPhone Mail (14F89) In-Reply-To: <2618aca3-c638-1496-7dbe-f865a17b1fbd@arm.com> Date: Fri, 4 Aug 2017 22:26:31 +0900 Cc: Russell King , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Message-Id: References: <1497232084-31907-1-git-send-email-hoeun.ryu@gmail.com> <1501826879.28554.47.camel@gmail.com> <2618aca3-c638-1496-7dbe-f865a17b1fbd@arm.com> To: Robin Murphy Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by nfs id v74DQf7o007401 2017. 8. 4. ¿ÀÈÄ 7:04 Robin Murphy ÀÛ¼º: >> On 04/08/17 07:07, Hoeun Ryu wrote: >> Hello, Russell King. >> >> The following patch has not merged yet. >> Do you have a plan to accept and merge this patch ? > > This should probably go through the ARM tree, so please submit it to > Russell's patch-tracking system here: > > http://www.armlinux.org.uk/developer/patches/ Thank you for the reply, I'll try it. > > Robin. > >> >> Thank you. >> >>> On Mon, 2017-06-12 at 10:47 +0900, Hoeun Ryu wrote: >>> Reading TTBCR in early boot stage might return the value of the previous >>> kernel's configuration, especially in case of kexec. For example, if >>> normal kernel (first kernel) had run on a configuration of PHYS_OFFSET <= >>> PAGE_OFFSET and crash kernel (second kernel) is running on a configuration >>> PHYS_OFFSET > PAGE_OFFSET, which can happen because it depends on the >>> reserved area for crash kernel, reading TTBCR and using the value to OR >>> other bit fields might be risky because it doesn't have a reset value for >>> TTBCR. >>> >>> Acked-by: Russell King >>> Suggested-by: Robin Murphy >>> Signed-off-by: Hoeun Ryu >>> >>> --- >>> >>> * add Acked-by: Russell King >>> * v1: amended based on >>> - "[PATCHv2] arm: LPAE: kexec: clear TTBCR.T1SZ explicitly when >>> PHYS_OFFSET > PAGE_OFFSET" >>> - https://lkml.org/lkml/2017/6/5/239 >>> >>> arch/arm/mm/proc-v7-3level.S | 3 +-- >>> 1 file changed, 1 insertion(+), 2 deletions(-) >>> >>> diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S >>> index 5e5720e..7d16bbc 100644 >>> --- a/arch/arm/mm/proc-v7-3level.S >>> +++ b/arch/arm/mm/proc-v7-3level.S >>> @@ -129,8 +129,7 @@ ENDPROC(cpu_v7_set_pte_ext) >>> .macro v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp >>> ldr \tmp, =swapper_pg_dir @ swapper_pg_dir virtual address >>> cmp \ttbr1, \tmp, lsr #12 @ PHYS_OFFSET > PAGE_OFFSET? >>> - mrc p15, 0, \tmp, c2, c0, 2 @ TTB control egister >>> - orr \tmp, \tmp, #TTB_EAE >>> + mov \tmp, #TTB_EAE @ for TTB control egister >>> ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP) >>> ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP) >>> ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP << 16) >