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Sun, 30 Jun 2024 11:11:10 GMT Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1F5852004B; Sun, 30 Jun 2024 11:11:08 +0000 (GMT) Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 76CB320043; Sun, 30 Jun 2024 11:11:05 +0000 (GMT) Received: from smtpclient.apple (unknown [9.43.36.144]) by smtpav01.fra02v.mail.ibm.com (Postfix) with ESMTPS; Sun, 30 Jun 2024 11:11:05 +0000 (GMT) Content-Type: text/plain; charset=utf-8 Subject: Re: [V4 05/16] tools/perf: Add disasm_line__parse to parse raw instruction for powerpc From: Athira Rajeev In-Reply-To: Date: Sun, 30 Jun 2024 16:40:53 +0530 Cc: Arnaldo Carvalho de Melo , Jiri Olsa , Adrian Hunter , Ian Rogers , Segher Boessenkool , Christophe Leroy , LKML , linux-perf-users , linuxppc-dev , akanksha@linux.ibm.com, Madhavan Srinivasan , Kajol Jain , Disha Goel Message-Id: References: <20240614172631.56803-1-atrajeev@linux.vnet.ibm.com> <20240614172631.56803-6-atrajeev@linux.vnet.ibm.com> <40DB645D-BFA7-44EA-B937-ADE81EEC1316@linux.vnet.ibm.com> To: Namhyung Kim X-Mailer: Apple Mail (2.3774.600.62) X-TM-AS-GCONF: 00 X-Proofpoint-GUID: yF1Csm4Lsa6coAMOsQ_I2TVGt19Yqz76 X-Proofpoint-ORIG-GUID: emi7M2YIlmbA1ktGayiGILEV9uVx7Rb0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-UnRewURL: 0 URL was un-rewritten Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-30_09,2024-06-28_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 clxscore=1015 phishscore=0 bulkscore=0 impostorscore=0 mlxscore=0 adultscore=0 mlxlogscore=999 suspectscore=0 malwarescore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406300085 > On 27 Jun 2024, at 2:47=E2=80=AFAM, Namhyung Kim wr= ote: >=20 > Hello, >=20 > On Wed, Jun 26, 2024 at 09:38:28AM +0530, Athira Rajeev wrote: >>=20 >>=20 >>> On 26 Jun 2024, at 12:15=E2=80=AFAM, Namhyung Kim = wrote: >>>=20 >>> On Tue, Jun 25, 2024 at 06:12:51PM +0530, Athira Rajeev wrote: >>>>=20 >>>>=20 >>>>> On 25 Jun 2024, at 11:09=E2=80=AFAM, Namhyung Kim wrote: >>>>>=20 >>>>> On Fri, Jun 14, 2024 at 10:56:20PM +0530, Athira Rajeev wrote: >>>>>> Currently, the perf tool infrastructure disasm_line__parse function = to >>>>>> parse disassembled line. >>>>>>=20 >>>>>> Example snippet from objdump: >>>>>> objdump --start-address=3D
--stop-address=3D
-d = --no-show-raw-insn -C >>>>>>=20 >>>>>> c0000000010224b4: lwz r10,0(r9) >>>>>>=20 >>>>>> This line "lwz r10,0(r9)" is parsed to extract instruction name, >>>>>> registers names and offset. In powerpc, the approach for data type >>>>>> profiling uses raw instruction instead of result from objdump to ide= ntify >>>>>> the instruction category and extract the source/target registers. >>>>>>=20 >>>>>> Example: 38 01 81 e8 ld r4,312(r1) >>>>>>=20 >>>>>> Here "38 01 81 e8" is the raw instruction representation. Add functi= on >>>>>> "disasm_line__parse_powerpc" to handle parsing of raw instruction. >>>>>> Also update "struct disasm_line" to save the binary code/ >>>>>> With the change, function captures: >>>>>>=20 >>>>>> line -> "38 01 81 e8 ld r4,312(r1)" >>>>>> raw instruction "38 01 81 e8" >>>>>>=20 >>>>>> Raw instruction is used later to extract the reg/offset fields. Macr= os >>>>>> are added to extract opcode and register fields. "struct disasm_line" >>>>>> is updated to carry union of "bytes" and "raw_insn" of 32 bit to car= ry raw >>>>>> code (raw). Function "disasm_line__parse_powerpc fills the raw >>>>>> instruction hex value and can use macros to get opcode. There is no >>>>>> changes in existing code paths, which parses the disassembled code. >>>>>> The architecture using the instruction name and present approach is >>>>>> not altered. Since this approach targets powerpc, the macro >>>>>> implementation is added for powerpc as of now. >>>>>>=20 >>>>>> Since the disasm_line__parse is used in other cases (perf annotate) = and >>>>>> not only data tye profiling, the powerpc callback includes changes to >>>>>> work with binary code as well as mneumonic representation. Also in c= ase >>>>>> if the DSO read fails and libcapstone is not supported, the approach >>>>>> fallback to use objdump as option. Hence as option, patch has change= s to >>>>>> ensure objdump option also works well. >>>>>>=20 >>>>>> Signed-off-by: Athira Rajeev >>>>>> --- > [SNIP] >>>>>> +/* >>>>>> + * Parses the result captured from symbol__disassemble_* >>>>>> + * Example, line read from DSO file in powerpc: >>>>>> + * line: 38 01 81 e8 >>>>>> + * opcode: fetched from arch specific get_opcode_insn >>>>>> + * rawp_insn: e8810138 >>>>>> + * >>>>>> + * rawp_insn is used later to extract the reg/offset fields >>>>>> + */ >>>>>> +#define PPC_OP(op) (((op) >> 26) & 0x3F) >>>>>> + >>>>>> +static int disasm_line__parse_powerpc(struct disasm_line *dl) >>>>>> +{ >>>>>> + char *line =3D dl->al.line; >>>>>> + const char **namep =3D &dl->ins.name; >>>>>> + char **rawp =3D &dl->ops.raw; >>>>>> + char tmp, *tmp_raw_insn, *name_raw_insn =3D skip_spaces(line); >>>>>> + char *name =3D skip_spaces(name_raw_insn + 11); >>>>>> + int objdump =3D 0; >>>>>> + >>>>>> + if (strlen(line) > 11) >>>>>> + objdump =3D 1; >>>>>> + >>>>>> + if (name_raw_insn[0] =3D=3D '\0') >>>>>> + return -1; >>>>>> + >>>>>> + if (objdump) { >>>>>> + *rawp =3D name + 1; >>>>>> + while ((*rawp)[0] !=3D '\0' && !isspace((*rawp)[0])) >>>>>> + ++*rawp; >>>>>> + tmp =3D (*rawp)[0]; >>>>>> + (*rawp)[0] =3D '\0'; >>>>>> + >>>>>> + *namep =3D strdup(name); >>>>>> + if (*namep =3D=3D NULL) >>>>>> + return -1; >>>>>> + >>>>>> + (*rawp)[0] =3D tmp; >>>>>> + *rawp =3D strim(*rawp); >>>>>> + } else >>>>>> + *namep =3D ""; >>>=20 >>> Then can you handle this logic under if (annotate_opts.show_raw_insn) >>> in disasm_line__parse() instead of adding a new function? >>>=20 >>> Thanks, >>> Namhyung >>=20 >> Hi Namhyung, >>=20 >> We discussed to have a per-arch disasm_line_parse() here: >> https://lore.kernel.org/all/CAM9d7ci1LDa7moT2qDr2qK+DTNLU6ZBkmROnbdozAju= QLQfNog@mail.gmail.com/#t >>=20 >> So I added it as a new function : disasm_line__parse_powerpc >> Since it is not used by other archs, we can go with having new function ? >=20 > Ok, I thought it'd be quite different from disasm_line__parse() but it > seems that it's mostly similar except for the raw insn. So I think it's > better to add the logic to the generic disasm_line__parse(). Sorry for > the inconvenience. >=20 > Thanks, > Namhyung Hi Namhyung I think it=E2=80=99s better to keep it as separate function. The field for = raw_insn and length differs from arch to arch ( powerpc is 32 bit instructi= on) . Also to handle cases where no objdump is used and only directly read from D= SO, disasm_line_parse needs some changes. Later for other archs to adopt DSO read or raw instruction or use different= way, its better we keep it separate function.=20 I will have it as separate function in V5 and include comment on what is th= e specific changes done compared to generic disasm_line__parse. Thanks Athira >=20 >>>>>> + >>>>>> + tmp_raw_insn =3D strdup(name_raw_insn); >>>>>> + tmp_raw_insn[11] =3D '\0'; >>>>>> + remove_spaces(tmp_raw_insn); >>>>>> + >>>>>> + dl->raw.raw_insn =3D strtol(tmp_raw_insn, NULL, 16); >>>>>> + if (objdump) >>>>>> + dl->raw.raw_insn =3D be32_to_cpu(strtol(tmp_raw_insn, NULL, 16)); >>>>>=20 >>>>> Hmm.. can you use a sscanf() instead? >>>>>=20 >>>>> sscanf(line, "%x %x %x %x", &dl->raw.bytes[0], &dl->raw.bytes[1], ...) >>>>>=20 >>>>> Thanks, >>>>> Namhyung >>>>>=20 >>>> Sure will address in V5 >>>>=20 >>>> Thanks >>>> Athira >>>>>> + >>>>>> + return 0; >>>>>> +}