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From: Tony Luck <tony.luck@intel.com>
To: Samuel Gabrielsson <samuel.gabrielsson@gmail.com>
Cc: mchehab@redhat.com, linux-edac@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] i7core_edac: Add scrubbing support
Date: Fri, 24 Jun 2011 14:47:37 -0700	[thread overview]
Message-ID: <BANLkTikyp-p8ymJvEmk2+=zsOZ1+JYYGMA@mail.gmail.com> (raw)
In-Reply-To: <1301491283-14128-2-git-send-email-samuel.gabrielsson@gmail.com>

On Wed, Mar 30, 2011 at 6:21 AM, Samuel Gabrielsson
<samuel.gabrielsson@gmail.com> wrote:
> +       const u32 cache_line_size = 64;
> +       const u32 freq_dclk = 800*1000000;

Is dclk always 800 MHz?  If so, a #define might me nice - you use it again in
get_sdram_scrub_rate(). If not, then getting the actual frequency from some
place would be good.

> +               dw_scrub = 0x00ffffff & (cache_line_size * freq_dclk / new_bw);

Does this give the right answer? It looks like you overflow the "u32" size
of these calculations when you do 64*800000000 = 51200000000.

> +       return 0xffffffff & (cache_line_size * freq_dclk / (u64) scrubval);

Ditto on the overflow question here.

-Tony

  parent reply	other threads:[~2011-06-24 21:47 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-03-30 13:21 [PATCH 1/2] i7core_edac: Add xeon 5600 generic non core registers Samuel Gabrielsson
2011-03-30 13:21 ` [PATCH 2/2] i7core_edac: Add scrubbing support Samuel Gabrielsson
2011-04-07 16:43   ` Nils Carlson
2011-06-24 21:47   ` Tony Luck [this message]
2011-07-22 14:06     ` Nils Carlson
2011-04-07 16:39 ` [PATCH 1/2] i7core_edac: Add xeon 5600 generic non core registers Nils Carlson

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