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From: Conor Dooley <conor@kernel.org>
To: Jisheng Zhang <jszhang@kernel.org>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/8] riscv: move riscv_noncoherent_supported() out of ZICBOM probe
Date: Thu, 13 Oct 2022 06:37:39 +0100	[thread overview]
Message-ID: <BBEFA528-0F84-41CB-A62F-ED4673947928@kernel.org> (raw)
In-Reply-To: <Y0GCST9IQcKws9Yh@xhacker>



On 8 October 2022 14:59:37 IST, Jisheng Zhang <jszhang@kernel.org> wrote:
>On Sat, Oct 08, 2022 at 02:06:00PM +0100, Conor Dooley wrote:
>> On Thu, Oct 06, 2022 at 03:08:11PM +0800, Jisheng Zhang wrote:
>> > It's a bit wired to call riscv_noncoherent_supported() once when
>> > insmod a module. Move the calling out of feature patch func.
>> > 
>> > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
>> > ---
>> >  arch/riscv/kernel/cpufeature.c | 7 +------
>> >  arch/riscv/kernel/setup.c      | 4 ++++
>> >  2 files changed, 5 insertions(+), 6 deletions(-)
>> > 
>> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
>> > index 3b5583db9d80..03611b3ef45e 100644
>> > --- a/arch/riscv/kernel/cpufeature.c
>> > +++ b/arch/riscv/kernel/cpufeature.c
>> > @@ -272,12 +272,7 @@ static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)
>> >  	case RISCV_ALTERNATIVES_EARLY_BOOT:
>> >  		return false;
>> >  	default:
>> > -		if (riscv_isa_extension_available(NULL, ZICBOM)) {
>> > -			riscv_noncoherent_supported();
>> > -			return true;
>> > -		} else {
>> > -			return false;
>> > -		}
>> > +		return riscv_isa_extension_available(NULL, ZICBOM);
>> >  	}
>> >  #endif
>> >  
>> > diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
>> > index 2dfc463b86bb..1a055c3f5d9d 100644
>> > --- a/arch/riscv/kernel/setup.c
>> > +++ b/arch/riscv/kernel/setup.c
>> > @@ -299,6 +299,10 @@ void __init setup_arch(char **cmdline_p)
>> >  	riscv_init_cbom_blocksize();
>> >  	riscv_fill_hwcap();
>> >  	apply_boot_alternatives();
>> > +#ifdef CONFIG_RISCV_DMA_NONCOHERENT
>> > +	if (riscv_isa_extension_available(NULL, ZICBOM))
>> > +		riscv_noncoherent_supported();
>> > +#endif
>> 
>> I have a personal bias against ifdefs where possible, maybe @Heiko
>> remembers why riscv_noncoherent_supported() was not defined as something
>> like `void riscv_noncoherent_support(void){}` for when that CONFIG is
>> not enabled? If it was this could become a an IS_ENABLED & we wouldn't
>> have to be so careful about wrapping it's usage in ifdefs.
>
>Good idea. Will do in newer version.

Given this comment and the LKP report I've marked the series as changes requested in patchwork FYI.

Thanks,
Conor.

>
>> 
>> Your change in isolation makes sense to me though, so:
>> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>> 
>> Thanks,
>> Conor.
>> 
>> >  }
>> >  
>> >  static int __init topology_init(void)
>> > -- 
>> > 2.37.2
>> > 

  reply	other threads:[~2022-10-13  5:37 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-06  7:08 [PATCH 0/8] riscv: improve boot time isa extensions handling Jisheng Zhang
2022-10-06  7:08 ` [PATCH 1/8] riscv: move riscv_noncoherent_supported() out of ZICBOM probe Jisheng Zhang
2022-10-06 13:10   ` Andrew Jones
2022-10-06 17:44     ` Andrew Jones
2022-10-07  9:18   ` Heiko Stübner
2022-10-08 13:06   ` Conor Dooley
2022-10-08 13:59     ` Jisheng Zhang
2022-10-13  5:37       ` Conor Dooley [this message]
2022-10-06  7:08 ` [PATCH 2/8] riscv: cpufeature: detect RISCV_ALTERNATIVES_EARLY_BOOT earlier Jisheng Zhang
2022-10-06 13:12   ` Andrew Jones
2022-10-07  9:38   ` Heiko Stübner
2022-10-06  7:08 ` [PATCH 3/8] riscv: hwcap: make ISA extension ids can be used in asm Jisheng Zhang
2022-10-06 13:15   ` Andrew Jones
2022-10-07  9:22   ` Heiko Stübner
2022-10-06  7:08 ` [PATCH 4/8] riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA extensions Jisheng Zhang
2022-10-06 13:31   ` Andrew Jones
2022-10-07 11:54   ` Heiko Stübner
2022-10-13 13:28     ` Heiko Stuebner
2022-10-06  7:08 ` [PATCH 5/8] riscv: introduce riscv_has_extension_[un]likely() Jisheng Zhang
2022-10-06 13:36   ` Andrew Jones
2022-10-06  7:08 ` [PATCH 6/8] riscv: fpu: switch has_fpu() to riscv_has_extension_likely() Jisheng Zhang
2022-10-06 13:36   ` Andrew Jones
2022-10-07 15:11   ` Heiko Stübner
2022-10-06  7:08 ` [PATCH 7/8] riscv: cpu_relax: switch " Jisheng Zhang
2022-10-06 13:28   ` kernel test robot
2022-10-06 13:37   ` Andrew Jones
2022-10-07 15:12   ` Heiko Stübner
2022-10-07 18:14   ` kernel test robot
2022-10-06  7:08 ` [PATCH 8/8] riscv: remove riscv_isa_ext_keys[] array and related usage Jisheng Zhang
2022-10-06 13:38   ` Andrew Jones
2022-10-07 15:12   ` Heiko Stübner
2022-10-13 16:20 ` [PATCH 0/8] riscv: improve boot time isa extensions handling Andrew Jones
2022-10-29  9:56 ` Andrew Jones
2022-10-29 11:38   ` Jisheng Zhang
2022-10-30 16:03   ` Jisheng Zhang

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