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[71.184.117.43]) by smtp.gmail.com with ESMTPSA id z18sm34006404qki.110.2019.08.05.05.03.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Aug 2019 05:03:11 -0700 (PDT) Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (Mac OS X Mail 12.4 \(3445.104.11\)) Subject: Re: [PATCH v2] arm64/prefetch: fix a -Wtype-limits warning From: Qian Cai In-Reply-To: <20190805100059.4gml6c4kclz2iin3@willie-the-truck> Date: Mon, 5 Aug 2019 08:03:10 -0400 Cc: Catalin Marinas , rrichter@cavium.com, robin.murphy@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Message-Id: References: <20190803003358.992-1-cai@lca.pw> <20190805100059.4gml6c4kclz2iin3@willie-the-truck> To: Will Deacon X-Mailer: Apple Mail (2.3445.104.11) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > On Aug 5, 2019, at 6:00 AM, Will Deacon wrote: >=20 > On Fri, Aug 02, 2019 at 08:33:58PM -0400, Qian Cai wrote: >> The commit d5370f754875 ("arm64: prefetch: add alternative pattern = for >> CPUs without a prefetcher") introduced MIDR_IS_CPU_MODEL_RANGE() to = be >> used in has_no_hw_prefetch() with rv_min=3D0 which generates a = compilation >> warning from GCC, >>=20 >> In file included from ./arch/arm64/include/asm/cache.h:8, >> from ./include/linux/cache.h:6, >> from ./include/linux/printk.h:9, >> from ./include/linux/kernel.h:15, >> from ./include/linux/cpumask.h:10, >> from arch/arm64/kernel/cpufeature.c:11: >> arch/arm64/kernel/cpufeature.c: In function 'has_no_hw_prefetch': >> ./arch/arm64/include/asm/cputype.h:59:26: warning: comparison of >> unsigned expression >=3D 0 is always true [-Wtype-limits] >> _model =3D=3D (model) && rv >=3D (rv_min) && rv <=3D (rv_max); \ >> ^~ >> arch/arm64/kernel/cpufeature.c:889:9: note: in expansion of macro >> 'MIDR_IS_CPU_MODEL_RANGE' >> return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, >> ^~~~~~~~~~~~~~~~~~~~~~~ >>=20 >> Fix it by making "rv" a "s32". >>=20 >> Signed-off-by: Qian Cai >> --- >>=20 >> v2: Use "s32" for "rv", so "variant 0/revision 0" can be covered. >>=20 >> arch/arm64/include/asm/cputype.h | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >>=20 >> diff --git a/arch/arm64/include/asm/cputype.h = b/arch/arm64/include/asm/cputype.h >> index e7d46631cc42..d52fe8651c2d 100644 >> --- a/arch/arm64/include/asm/cputype.h >> +++ b/arch/arm64/include/asm/cputype.h >> @@ -54,7 +54,7 @@ >> #define MIDR_IS_CPU_MODEL_RANGE(midr, model, rv_min, rv_max) = \ >> ({ = \ >> u32 _model =3D (midr) & MIDR_CPU_MODEL_MASK; = \ >> - u32 rv =3D (midr) & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK); = \ >> + s32 rv =3D (midr) & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK); = \ >=20 > Hmm, but this really isn't a signed quantity: it's two fields = extracted > from an ID register. I think the code is fine. Are you explicitly = enabling > -Wtype-limits somehow? Yes, it is useful to catch unintended developer mistakes or simply = optimize wasted instructions of checking like in, 919aef44d73d (=E2=80=9Cx86/efi: fix a -Wtype-limits compilation = warning=E2=80=9D) 5a82bdb48f04 (=E2=80=9Cx86/cacheinfo: Fix a -Wtype-limits warning=E2=80=9D= ) It is normal to fix a false positive this way as in other mainline = commits, ec6335586953 (=E2=80=9Cx86/apic: Silence -Wtype-limits compiler = warnings=E2=80=9D) Once those false-positives are under control, the warning flag could be = then enabled by default in the future.