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Mon, 8 Dec 2025 15:40:34 +0000 Received: from DS7PR19MB8883.namprd19.prod.outlook.com ([fe80::5880:19f:c819:c921]) by DS7PR19MB8883.namprd19.prod.outlook.com ([fe80::5880:19f:c819:c921%5]) with mapi id 15.20.9388.013; Mon, 8 Dec 2025 15:40:34 +0000 Message-ID: Date: Mon, 8 Dec 2025 19:40:21 +0400 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v19 2/6] pwm: driver for qualcomm ipq6018 pwm block To: Konrad Dybcio , =?UTF-8?Q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Devi Priya , Baruch Siach References: <20251128-ipq-pwm-v19-0-13bc704cc6a5@outlook.com> <20251128-ipq-pwm-v19-2-13bc704cc6a5@outlook.com> <3aa86b13-9505-4f64-a168-4c46962b715e@oss.qualcomm.com> Content-Language: en-US From: George Moussalem In-Reply-To: <3aa86b13-9505-4f64-a168-4c46962b715e@oss.qualcomm.com> Content-Type: text/plain; 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Based on >> driver from downstream Codeaurora kernel tree. Removed support for older >> (V1) variants because I have no access to that hardware. >> >> Tested on IPQ5018 and IPQ6010 based hardware. >> >> Co-developed-by: Baruch Siach >> Signed-off-by: Baruch Siach >> Signed-off-by: Devi Priya >> Reviewed-by: Bjorn Andersson >> Signed-off-by: George Moussalem >> --- > > [...] > >> +/* The frequency range supported is 1 Hz to clock rate */ >> +#define IPQ_PWM_MAX_PERIOD_NS ((u64)NSEC_PER_SEC) >> + >> +/* >> + * The max value specified for each field is based on the number of bits >> + * in the pwm control register for that field >> + */ >> +#define IPQ_PWM_MAX_DIV 0xFFFF >> + >> +/* >> + * Two 32-bit registers for each PWM: REG0, and REG1. >> + * Base offset for PWM #i is at 8 * #i. >> + */ >> +#define IPQ_PWM_REG0 0 >> +#define IPQ_PWM_REG0_PWM_DIV GENMASK(15, 0) >> +#define IPQ_PWM_REG0_HI_DURATION GENMASK(31, 16) >> + >> +#define IPQ_PWM_REG1 4 >> +#define IPQ_PWM_REG1_PRE_DIV GENMASK(15, 0) > > Sorry for coming in so late, you may consider this as material for a > follow-up patch (I *really* don't want to hold off your v19..) > > I see that on ipq9574 the registers are named: > > base = 0x1941010 = tcsr + 0xa010 > > 0x0 CFG0_R0 > 0x4 CFG1_R0 > 0x8 CFG0_R1 > 0xc CFG1_R1 > 0x10 CFG0_R2 > 0x14 CFG1_R2 > 0x18 CFG0_R3 > 0x1c CFG1_R3 > > CFG0 and CFG1 are what you called REG0/REG1 and Rn is confusingly the > index of the controller/output > > The other bits in CFG1 (29:16) are RESERVED so there's nothing you > missed in there thanks for your review and validation. > >> + >> +/* >> + * Enable bit is set to enable output toggling in pwm device. >> + * Update bit is set to trigger the change and is unset automatically >> + * to reflect the changed divider and high duration values in register. >> + */ >> +#define IPQ_PWM_REG1_UPDATE BIT(30) >> +#define IPQ_PWM_REG1_ENABLE BIT(31) >> + >> +struct ipq_pwm_chip { >> + struct clk *clk; >> + void __iomem *mem; >> +}; >> + >> +static struct ipq_pwm_chip *ipq_pwm_from_chip(struct pwm_chip *chip) >> +{ >> + return pwmchip_get_drvdata(chip); >> +} >> + >> +static unsigned int ipq_pwm_reg_read(struct pwm_device *pwm, unsigned int reg) >> +{ >> + struct ipq_pwm_chip *ipq_chip = ipq_pwm_from_chip(pwm->chip); >> + unsigned int off = 8 * pwm->hwpwm + reg; > > This magic 8 could be #defined as IPQ6018_PWM_CONTROLLER_STRIDE or so good suggestion, will add it should another iteration be required. > > Konrad BR, George