From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753262Ab1BOAvj (ORCPT ); Mon, 14 Feb 2011 19:51:39 -0500 Received: from blu0-omc1-s20.blu0.hotmail.com ([65.55.116.31]:48480 "EHLO blu0-omc1-s20.blu0.hotmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751217Ab1BOAvh (ORCPT ); Mon, 14 Feb 2011 19:51:37 -0500 X-Originating-IP: [174.91.193.52] X-Originating-Email: [pdumas9@sympatico.ca] Message-ID: Date: Mon, 14 Feb 2011 19:51:28 -0500 From: Mathieu Desnoyers To: "Paul E. McKenney" CC: Matt Fleming , David Miller , rostedt@goodmis.org, peterz@infradead.org, will.newton@gmail.com, jbaron@redhat.com, hpa@zytor.com, mingo@elte.hu, tglx@linutronix.de, andi@firstfloor.org, roland@redhat.com, rth@redhat.com, masami.hiramatsu.pt@hitachi.com, fweisbec@gmail.com, avi@redhat.com, sam@ravnborg.org, ddaney@caviumnetworks.com, michael@ellerman.id.au, linux-kernel@vger.kernel.org, vapier@gentoo.org, cmetcalf@tilera.com, dhowells@redhat.com, schwidefsky@de.ibm.com, heiko.carstens@de.ibm.com, benh@kernel.crashing.org, Segher Boessenkool , Paul Mackerras Subject: Re: [PATCH 0/2] jump label: 2.6.38 updates References: <1297707868.5226.189.camel@laptop> <1297718964.23343.75.camel@gandalf.stny.rr.com> <1297719576.23343.80.camel@gandalf.stny.rr.com> <20110214.134600.179933733.davem@davemloft.net> <20110214223755.436e7cf4@mfleming-mobl1.ger.corp.intel.com> <20110214230902.GM2256@linux.vnet.ibm.com> <20110215004259.GP2256@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Content-Disposition: inline In-Reply-To: <20110215004259.GP2256@linux.vnet.ibm.com> X-Editor: vi X-Info: http://krystal.dyndns.org:8080 X-Operating-System: Linux/2.6.27.31-grsec (i686) X-Uptime: 19:49:16 up 313 days, 10:38, 5 users, load average: 2.15, 2.05, 1.92 User-Agent: Mutt/1.5.18 (2008-05-17) X-OriginalArrivalTime: 15 Feb 2011 00:51:35.0482 (UTC) FILETIME=[7ED891A0:01CBCCAA] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Paul E. McKenney (paulmck@linux.vnet.ibm.com) wrote: > On Mon, Feb 14, 2011 at 06:29:47PM -0500, Mathieu Desnoyers wrote: > > [ added Segher Boessenkool and Paul Mackerras to CC list ] > > > > * Paul E. McKenney (paulmck@linux.vnet.ibm.com) wrote: > > > On Mon, Feb 14, 2011 at 06:03:01PM -0500, Mathieu Desnoyers wrote: > > > > * Matt Fleming (matt@console-pimps.org) wrote: > > > > > On Mon, 14 Feb 2011 13:46:00 -0800 (PST) > > > > > David Miller wrote: > > > > > > > > > > > From: Steven Rostedt > > > > > > Date: Mon, 14 Feb 2011 16:39:36 -0500 > > > > > > > > > > > > > Thus it is not about global, as global is updated by normal means > > > > > > > and will update the caches. atomic_t is updated via the ll/sc that > > > > > > > ignores the cache and causes all this to break down. IOW... broken > > > > > > > hardware ;) > > > > > > > > > > > > I don't see how cache coherency can possibly work if the hardware > > > > > > behaves this way. > > > > > > > > > > Cache coherency is still maintained provided writes/reads both go > > > > > through the cache ;-) > > > > > > > > > > The problem is that for read-modify-write operations the arbitration > > > > > logic that decides who "wins" and is allowed to actually perform the > > > > > write, assuming two or more CPUs are competing for a single memory > > > > > address, is not implemented in the cache controller, I think. I'm not a > > > > > hardware engineer and I never understood how the arbitration logic > > > > > worked but I'm guessing that's the reason that the ll/sc instructions > > > > > bypass the cache. > > > > > > > > > > Which is why the atomic_t functions worked out really well for that > > > > > arch, such that any accesses to an atomic_t * had to go through the > > > > > wrapper functions. > > > > > > ??? > > > > > > What CPU family are we talking about here? For cache coherent CPUs, > > > cache coherence really is supposed to work, even for mixed atomic and > > > non-atomic instructions to the same variable. > > > > > > > I'm really curious to know which CPU families too. I've used git blame > > to see where these lwz/stw instructions were added to powerpc, and it > > points to: > > But lwz and stw instructions are normal non-atomic PowerPC loads and > stores. No LL/SC -- those would instead be lwarx and stwcx. Ah, right. Color me confused ;) I think Matt was talking about a secret "out of tree" architecture. It sure feels like a James Bond movie. :) Thanks, Mathieu > > Thanx, Paul > > > commit 9f0cbea0d8cc47801b853d3c61d0e17475b0cc89 > > Author: Segher Boessenkool > > Date: Sat Aug 11 10:15:30 2007 +1000 > > > > [POWERPC] Implement atomic{, 64}_{read, write}() without volatile > > > > Instead, use asm() like all other atomic operations already do. > > > > Also use inline functions instead of macros; this actually > > improves code generation (some code becomes a little smaller, > > probably because of improved alias information -- just a few > > hundred bytes total on a default kernel build, nothing shocking). > > > > Signed-off-by: Segher Boessenkool > > Signed-off-by: Paul Mackerras > > > > So let's ping the relevant people to see if there was any reason for > > making these atomic read/set operations different from other > > architectures in the first place. > > > > Thanks, > > > > Mathieu > > > > -- > > Mathieu Desnoyers > > Operating System Efficiency R&D Consultant > > EfficiOS Inc. > > http://www.efficios.com -- Mathieu Desnoyers Operating System Efficiency R&D Consultant EfficiOS Inc. http://www.efficios.com