From: Chen Wang <unicorn_wang@outlook.com>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
Chen Wang <unicornxw@gmail.com>
Cc: kw@linux.com, u.kleine-koenig@baylibre.com,
aou@eecs.berkeley.edu, arnd@arndb.de, bhelgaas@google.com,
conor+dt@kernel.org, guoren@kernel.org, inochiama@outlook.com,
krzk+dt@kernel.org, lee@kernel.org, lpieralisi@kernel.org,
palmer@dabbelt.com, paul.walmsley@sifive.com,
pbrobinson@gmail.com, robh@kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org, linux-riscv@lists.infradead.org,
chao.wei@sophgo.com, xiaoguang.xing@sophgo.com,
fengchun.li@sophgo.com, helgaas@kernel.org
Subject: Re: [PATCH v3 1/5] dt-bindings: pci: Add Sophgo SG2042 PCIe host
Date: Wed, 22 Jan 2025 20:52:39 +0800 [thread overview]
Message-ID: <BM1PR01MB25450B47C36ADE01F53CAFD1FEE12@BM1PR01MB2545.INDPRD01.PROD.OUTLOOK.COM> (raw)
In-Reply-To: <20250119114408.3ma4itsjyxki74h4@thinkpad>
On 2025/1/19 19:44, Manivannan Sadhasivam wrote:
> On Wed, Jan 15, 2025 at 03:06:37PM +0800, Chen Wang wrote:
>> From: Chen Wang <unicorn_wang@outlook.com>
>>
>> Add binding for Sophgo SG2042 PCIe host controller.
>>
>> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
>> ---
>> .../bindings/pci/sophgo,sg2042-pcie-host.yaml | 147 ++++++++++++++++++
>> 1 file changed, 147 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
[......]
>> +examples:
>> + - |
>> + #include <dt-bindings/interrupt-controller/irq.h>
>> +
>> + pcie@62000000 {
>> + compatible = "sophgo,sg2042-pcie-host";
>> + device_type = "pci";
>> + reg = <0x62000000 0x00800000>,
>> + <0x48000000 0x00001000>;
> Use single space between address and size.
ok, thanks.
>> + reg-names = "reg", "cfg";
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>,
>> + <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
> For sure you don't need to set 'relocatable' flag for both regions.
ok, I will correct this in next version.
>> + bus-range = <0x00 0xff>;
>> + vendor-id = <0x1f1c>;
>> + device-id = <0x2042>;
> As Bjorn explained in v2, these properties need to be moved to PCI root port
> node. Your argument of a single root port node for a host bridge doesn't add as
> we have found that describing the root port properties in host bridge only
> creates issues.
Got it. I will try to change this in next version.
> Btw, we are migrating the existing single RP platforms too to root port node.
>
>> + cdns,no-bar-match-nbits = <48>;
>> + sophgo,link-id = <0>;
>> + sophgo,syscon-pcie-ctrl = <&cdns_pcie1_ctrl>;
> Where is the num-lanes property?
Is this num-lanes a must-have property? The lane number of each link on
the SG2042 is hard-coded in the firmware, so it seems meaningless to
configure it.
>> + msi-parent = <&msi_pcie>;
>> + msi_pcie: msi {
> 'msi' is not a standard node name. 'interrupt-controller' is what usually used
> to describe the MSI node.
OK. I will corret this.
> Btw, is the MSI controller a separate IP inside the host bridge? If not, there
> would no need to add a separate node. Most of the host bridge IPs implementing
> MSI controller, do not use a separate node.
Yes, it's a separated IP inside the host bridge.
> - Mani
Thanks,
Chen
next prev parent reply other threads:[~2025-01-22 12:52 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-15 7:05 [PATCH v3 0/5] Add PCIe support to Sophgo SG2042 SoC Chen Wang
2025-01-15 7:06 ` [PATCH v3 1/5] dt-bindings: pci: Add Sophgo SG2042 PCIe host Chen Wang
2025-01-19 11:44 ` Manivannan Sadhasivam
2025-01-22 12:52 ` Chen Wang [this message]
2025-01-22 17:21 ` Manivannan Sadhasivam
2025-01-26 0:29 ` Chen Wang
2025-01-22 22:21 ` Bjorn Helgaas
2025-01-26 2:27 ` Chen Wang
2025-02-03 2:35 ` Chen Wang
2025-02-11 23:34 ` Bjorn Helgaas
2025-02-12 1:50 ` Chen Wang
2025-02-12 4:25 ` Bjorn Helgaas
2025-02-12 5:54 ` Chen Wang
2025-02-17 8:40 ` Chen Wang
2025-02-19 18:22 ` Bjorn Helgaas
2025-02-21 3:29 ` Chen Wang
2025-02-21 22:13 ` Bjorn Helgaas
2025-02-24 6:27 ` Manivannan Sadhasivam
2025-01-15 7:06 ` [PATCH v3 2/5] PCI: sg2042: Add Sophgo SG2042 PCIe driver Chen Wang
2025-01-19 12:23 ` Manivannan Sadhasivam
2025-01-22 13:28 ` Chen Wang
2025-01-22 17:34 ` Manivannan Sadhasivam
2025-01-23 12:12 ` Marc Zyngier
2025-02-07 17:49 ` Manivannan Sadhasivam
2025-02-17 8:22 ` Chen Wang
2025-02-19 17:57 ` Manivannan Sadhasivam
2025-01-22 21:33 ` Bjorn Helgaas
2025-02-17 8:36 ` Chen Wang
2025-01-15 7:07 ` [PATCH v3 3/5] dt-bindings: mfd: syscon: Add sg2042 pcie ctrl compatible Chen Wang
2025-02-11 14:33 ` (subset) " Lee Jones
2025-02-12 0:48 ` Chen Wang
2025-02-20 16:00 ` Lee Jones
2025-01-15 7:07 ` [PATCH v3 4/5] riscv: sophgo: dts: add pcie controllers for SG2042 Chen Wang
2025-01-15 7:07 ` [PATCH v3 5/5] riscv: sophgo: dts: enable pcie for PioneerBox Chen Wang
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