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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BY5PR11MB4306.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2084ced3-1013-4c26-f1fd-08dbb0712178 X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Sep 2023 13:40:14.1866 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: DfN66AN7jLEyUpTlcmmJMKJZFL/lcmYEwqSd6r4lafWxVywE0zhMhpDhyPIbOKIMuZfdUBqNlQ4vOYNjslTIOHFpuJXSP5dFUWPn0lw3Q9M= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR11MB5360 X-OriginatorOrg: intel.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Bjorn Helgaas > Sent: Friday, September 8, 2023 6:14 PM > To: D M, Sharath Kumar > Cc: lpieralisi@kernel.org; kw@linux.com; robh@kernel.org; > bhelgaas@google.com; linux-pci@vger.kernel.org; dinguyen@kernel.org; > linux-kernel@vger.kernel.org > Subject: Re: [PATCH v2 1/2] PCI: altera: refactor driver for supporting n= ew > platform >=20 > On Fri, Sep 08, 2023 at 09:09:34AM +0000, D M, Sharath Kumar wrote: > > > -----Original Message----- > > > From: Bjorn Helgaas ... >=20 > > > > + int (*ep_read_cfg)(struct altera_pcie *pcie, u8 busno, > > > > + unsigned int devfn, int where, int size, u32 *value); > > > > + int (*ep_write_cfg)(struct altera_pcie *pcie, u8 busno, > > > > + unsigned int devfn, int where, int size, u32 value); > > > > > > "ep_read_cfg" isn't the ideal name because it suggests "endpoint", > > > but it may be either an endpoint or a switch upstream port. The > > > rockchip driver uses "other", which isn't super descriptive either bu= t > might be better. > > > > > Ok will change to "nonrp_read_cfg" ? >=20 > I think the important point is not whether it's a Root Port or not, but w= hether > it's on the root *bus* or not. In other words, I think the driver has to > determine whether to generate a Type 0 (targeting something on the root > bus) or a Type 1 (targeting something below a > bridge) config transaction (see PCI-to-PCI Bridge spec r1.2, sec 3.1.2.1)= . >=20 > There can be non-Root Ports on the root bus, so "nonrp" doesn't seem quit= e > right. "Other" would be OK, since that's already used by other drivers. > Maybe "type0" and "type1" would be better and would fit well with the > root_bus_nr check you use to distinguish them? >=20 Situation is Root port configuration space - memory mapped Non root port configuration space - indirect access/proprietary access Type 0 for devices directly connected to root port Type 1 for others > > > > +static int _altera_pcie_cfg_read(struct altera_pcie *pcie, u8 busn= o, > > > > + unsigned int devfn, int where, int size, > > > > + u32 *value) > > > > +{ > > > > + if (busno =3D=3D pcie->root_bus_nr && pcie->pcie_data->ops- > > > >rp_read_cfg) > > > > + return pcie->pcie_data->ops->rp_read_cfg(pcie, busno, > > > devfn, > > > > + where, size, value); > > > > + > > > > + if (pcie->pcie_data->ops->ep_read_cfg) > > > > + return pcie->pcie_data->ops->ep_read_cfg(pcie, busno, > > > devfn, > > > > + where, size, value); > > > > + return PCIBIOS_FUNC_NOT_SUPPORTED; }