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Mon, 30 Mar 2020 09:37:42 +0000 From: Bharat Kumar Gogada To: "lorenzo.pieralisi@arm.com" , "maz@kernel.org" CC: "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , Ravikiran Gummaluri Subject: RE: [PATCH v5 2/2] PCI: xilinx-cpm: Add Versal CPM Root Port driver Thread-Topic: [PATCH v5 2/2] PCI: xilinx-cpm: Add Versal CPM Root Port driver Thread-Index: AQHV14gyqXPkldKNt0SLTelX37u03Kgr8Z6AgAAlV5CABIIlAIAaXfLggBZHSCA= Date: Mon, 30 Mar 2020 09:37:42 +0000 Message-ID: References: <1580400771-12382-1-git-send-email-bharat.kumar.gogada@xilinx.com> <1580400771-12382-3-git-send-email-bharat.kumar.gogada@xilinx.com> <20200225114013.GB6913@e121166-lin.cambridge.arm.com> <20200228104442.GA2874@e121166-lin.cambridge.arm.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=bharatku@xilinx.com; x-originating-ip: [149.199.50.129] x-ms-publictraffictype: Email x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: adeb3adf-fa9c-4cba-f946-08d7d48dfecb x-ms-traffictypediagnostic: BYAPR02MB5045:|BYAPR02MB5045: x-ld-processed: 657af505-d5df-48d0-8300-c31994686c5c,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:9508; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-Network-Message-Id: adeb3adf-fa9c-4cba-f946-08d7d48dfecb X-MS-Exchange-CrossTenant-originalarrivaltime: 30 Mar 2020 09:37:42.4700 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: ytrt4Xu+VG3vkSoXbx5VZQ5YZsPOIwzS0LiEfJIepCfgfiU9SfBFJue+Pl9ohLVJ90zOq4KyUMVKUyp8s3ZhZw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR02MB5045 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > Subject: RE: [PATCH v5 2/2] PCI: xilinx-cpm: Add Versal CPM Root Port dri= ver >=20 > > Subject: Re: [PATCH v5 2/2] PCI: xilinx-cpm: Add Versal CPM Root Port > > driver > > > > [+MarcZ, FHI] > > > > On Tue, Feb 25, 2020 at 02:39:56PM +0000, Bharat Kumar Gogada wrote: > > > > [...] > > > > > > > +/* ECAM definitions */ > > > > > +#define ECAM_BUS_NUM_SHIFT 20 > > > > > +#define ECAM_DEV_NUM_SHIFT 12 > > > > > > > > You don't need these ECAM_* defines, you can use pci_generic_ecam_o= ps. > > > Does this need separate ranges region for ECAM space ? > > > We have ECAM and controller space in same region. > > > > You can create an ECAM window with pci_ecam_create where *cfgres > > represent the ECAM area, I don't get what you mean by "same region". > > > > Do you mean "contiguous" ? Or something else ? > > > > > > > + > > > > > +/** > > > > > + * struct xilinx_cpm_pcie_port - PCIe port information > > > > > + * @reg_base: Bridge Register Base > > > > > + * @cpm_base: CPM System Level Control and Status > > > > > +Register(SLCR) Base > > > > > + * @irq: Interrupt number > > > > > + * @root_busno: Root Bus number > > > > > + * @dev: Device pointer > > > > > + * @leg_domain: Legacy IRQ domain pointer > > > > > + * @irq_misc: Legacy and error interrupt number */ struct > > > > > +xilinx_cpm_pcie_port { > > > > > + void __iomem *reg_base; > > > > > + void __iomem *cpm_base; > > > > > + u32 irq; > > > > > + u8 root_busno; > > > > > + struct device *dev; > > > > > + struct irq_domain *leg_domain; > > > > > + int irq_misc; > > > > > +}; > > > > > + > > > > > +static inline u32 pcie_read(struct xilinx_cpm_pcie_port *port, > > > > > +u32 > > > > > +reg) { > > > > > + return readl(port->reg_base + reg); } > > > > > + > > > > > +static inline void pcie_write(struct xilinx_cpm_pcie_port *port, > > > > > + u32 val, u32 reg) > > > > > +{ > > > > > + writel(val, port->reg_base + reg); } > > > > > + > > > > > +static inline bool cpm_pcie_link_up(struct xilinx_cpm_pcie_port > > > > > +*port) { > > > > > + return (pcie_read(port, XILINX_CPM_PCIE_REG_PSCR) & > > > > > + XILINX_CPM_PCIE_REG_PSCR_LNKUP) ? 1 : 0; > > > > > > > > u32 val =3D pcie_read(port, XILINX_CPM_PCIE_REG_PSCR); > > > > > > > > return val & XILINX_CPM_PCIE_REG_PSCR_LNKUP; > > > > > > > > And this function call is not that informative anyway - it is used > > > > just to print a log whose usefulness is questionable. > > > We need this logging information customers are using this info in > > > case of link down failure. > > > > Out of curiosity, to do what ? > > > > [...] > > > > > > > +/** > > > > > + * xilinx_cpm_pcie_intx_map - Set the handler for the INTx and > > > > > +mark IRQ as valid > > > > > + * @domain: IRQ domain > > > > > + * @irq: Virtual IRQ number > > > > > + * @hwirq: HW interrupt number > > > > > + * > > > > > + * Return: Always returns 0. > > > > > + */ > > > > > +static int xilinx_cpm_pcie_intx_map(struct irq_domain *domain, > > > > > + unsigned int irq, irq_hw_number_t > hwirq) { > > > > > + irq_set_chip_and_handler(irq, &dummy_irq_chip, > > > > > +handle_simple_irq); > > > > > > > > INTX are level IRQs, the flow handler must be handle_level_irq. > > > Accepted will change. > > > > > > > > > + irq_set_chip_data(irq, domain->host_data); > > > > > + irq_set_status_flags(irq, IRQ_LEVEL); > > > > > > > > The way INTX are handled in this patch is wrong. You must set-up a > > > > chained IRQ with the appropriate flow handler, current code uses > > > > an IRQ action and that's an IRQ layer violation and it goes > > > > without saying that it > > is almost certainly broken. > > > In our controller we use same irq line for controller errors and > > > legacy errors. we have two cases here where error interrupts are > > > self-consumed by controller, and legacy interrupts are flow handled. > > > Its not INTX handling alone for this IRQ line . So chained IRQ can > > > be used for self consumed interrupts too ? > > > > No. In this specific case both solutions are not satisfying, we need > > to give it some thought, I will talk to Marc (CC'ed) to find the best > > option here going forward. > > > Hi Marc, >=20 > Can you please provide yours inputs for this case. >=20 Hi Marc, Can you please provide required inputs on this. Regards, Bharat