RE: [PATCH v9 2/2] PCI: xilinx-cpm: Add Versal CPM Root Port driver

[Bharat Kumar Gogada <bharatku@xilinx.com>]

> Subject: Re: [PATCH v9 2/2] PCI: xilinx-cpm: Add Versal CPM Root Port driver
> 
> On Fri, Jul 10, 2020 at 09:16:57AM -0600, Rob Herring wrote:
> > On Tue, Jun 16, 2020 at 6:57 AM Bharat Kumar Gogada
> > <bharat.kumar.gogada@xilinx.com> wrote:
> > >
> > > - Add support for Versal CPM as Root Port.
> > > - The Versal ACAP devices include CCIX-PCIe Module (CPM). The
> integrated
> > >   block for CPM along with the integrated bridge can function
> > >   as PCIe Root Port.
> > > - Bridge error and legacy interrupts in Versal CPM are handled using
> > >   Versal CPM specific interrupt line.
> > >
> > > Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
> > > ---
> > >  drivers/pci/controller/Kconfig           |   8 +
> > >  drivers/pci/controller/Makefile          |   1 +
> > >  drivers/pci/controller/pcie-xilinx-cpm.c | 617
> > > +++++++++++++++++++++++++++++++
> > >  3 files changed, 626 insertions(+)
> > >  create mode 100644 drivers/pci/controller/pcie-xilinx-cpm.c
> >
> > [...]
> >
> > > +static int xilinx_cpm_pcie_probe(struct platform_device *pdev) {
> > > +       struct xilinx_cpm_pcie_port *port;
> > > +       struct device *dev = &pdev->dev;
> > > +       struct pci_host_bridge *bridge;
> > > +       struct resource *bus_range;
> > > +       int err;
> > > +
> > > +       bridge = devm_pci_alloc_host_bridge(dev, sizeof(*port));
> > > +       if (!bridge)
> > > +               return -ENODEV;
> > > +
> > > +       port = pci_host_bridge_priv(bridge);
> > > +
> > > +       port->dev = dev;
> > > +
> > > +       err = pci_parse_request_of_pci_ranges(dev, &bridge->windows,
> > > +                                             &bridge->dma_ranges, &bus_range);
> > > +       if (err) {
> > > +               dev_err(dev, "Getting bridge resources failed\n");
> > > +               return err;
> > > +       }
> > > +
> > > +       err = xilinx_cpm_pcie_init_irq_domain(port);
> > > +       if (err)
> > > +               return err;
> > > +
> > > +       err = xilinx_cpm_pcie_parse_dt(port, bus_range);
> > > +       if (err) {
> > > +               dev_err(dev, "Parsing DT failed\n");
> > > +               goto err_parse_dt;
> > > +       }
> > > +
> > > +       xilinx_cpm_pcie_init_port(port);
> > > +
> > > +       err = xilinx_cpm_setup_irq(port);
> > > +       if (err) {
> > > +               dev_err(dev, "Failed to set up interrupts\n");
> > > +               goto err_setup_irq;
> > > +       }
> >
> > All the h/w init here can be moved to an .init() function in ecam ops
> > and then use pci_host_common_probe. Given this is v9, that can be a
> > follow-up I guess.
> 
> I think there is time to get it done, Bharat please let me know if you can
> repost it shortly with Rob's requested change implemented.
>
Thanks Rob for your time.
Thanks Lorenzo, the reason I cannot use pci_host_common_probe is, 
I need pci_config_window locally as the we use same ecam space for local bridge register access.
In xilinx_cpm_pcie_parse_dt funciton
port->reg_base = port->cfg->win;

If we move to pci_host_common_probe, I will not be able to access controller registers.
So can we please proceed with existing flow. 

Regards,
Bharat

> >
> > > +
> > > +       bridge->dev.parent = dev;
> > > +       bridge->sysdata = port->cfg;
> > > +       bridge->busnr = port->cfg->busr.start;
> > > +       bridge->ops = &pci_generic_ecam_ops.pci_ops;
> > > +       bridge->map_irq = of_irq_parse_and_map_pci;
> > > +       bridge->swizzle_irq = pci_common_swizzle;
> > > +
> > > +       err = pci_host_probe(bridge);
> > > +       if (err < 0)
> > > +               goto err_host_bridge;
> > > +
> > > +       return 0;
> > > +
> > > +err_host_bridge:
> > > +       xilinx_cpm_free_interrupts(port);
> > > +err_setup_irq:
> > > +       pci_ecam_free(port->cfg);
> > > +err_parse_dt:
> > > +       xilinx_cpm_free_irq_domains(port);
> > > +       return err;
> > > +}