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Wed, 9 Sep 2020 15:46:13 +0000 From: Manish Narani To: Rob Herring CC: "gregkh@linuxfoundation.org" , Michal Simek , "balbi@kernel.org" , "p.zabel@pengutronix.de" , "linux-usb@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , git Subject: RE: [PATCH 1/2] dt-bindings: usb: dwc3-xilinx: Add documentation for Versal DWC3 Controller Thread-Topic: [PATCH 1/2] dt-bindings: usb: dwc3-xilinx: Add documentation for Versal DWC3 Controller Thread-Index: AQHWe9j+PlxSy8oZg0WQBIs3MmmIKKlfcVoAgAEWjJA= Date: Wed, 9 Sep 2020 15:46:13 +0000 Message-ID: References: <1598467441-124203-1-git-send-email-manish.narani@xilinx.com> <1598467441-124203-2-git-send-email-manish.narani@xilinx.com> <20200908230520.GA1102401@bogus> In-Reply-To: <20200908230520.GA1102401@bogus> Accept-Language: en-IN, en-US Content-Language: en-US X-MS-Has-Attach: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-TNEF-Correlator: authentication-results: kernel.org; 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x-ms-exchange-antispam-messagedata: 9CTfkpjQMdi85PmN01LU+zmO7s0aVqUSX0M7aZ/UawyFyB3CFQAkPn9cm3Oxb81iGMNItD/mmalAglNLTCye5GhCR5ru/jg5RCCGTF6/Oc5JikW0pwBxU9OHP0h3u8Xhar6OLAHl+9BNboWiDx8h3zjz93pim72dx7xAunM2iGbgbKLdz0KtdWj40hedKVyQD8ONeZvHf4ii0Ygh1GDiSLmkl/o+vQSkl5gJMM2QudxrE0Bi/yeTBei6Szo8oHK13azEthkhIT0RldwQcRKutv8J24Q18gxX4I97VqNvJL2nWA0Ld4XwoDb9cW+KEZS9hSp3dSBCBskNryCl+uuoiavBcBbuf0fqZBrXDlv4KFW0bFZiPAkVPNWhCuvIShMvnyULT0YALJ3UGd+WkY3BAZFkoOO0Y8pPHWZEDME3+MI6SJrTi36VIUqC5nMVbW3zUnefTN+P0W5I2JdzAg8GpE5sNx4u0jyHEuePuEeyxGluq+rvR1xVbuE2vtyxSY1Jscw49t9igaQtdTRk/skEGmSVPc7DTJHpldbKbPDuuWgn7F33S3ULQa2gBD/+yvGWOGgS/9pKVlrwhb0nUlUlmcUCtpI4xJ2Ozmevw3u9URXnuJbUoCspllXAQNPNF3evvEh6Gl2JJbB0i/tQf7aapw== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BYAPR02MB5896.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6e7f3652-0efe-4840-f709-08d854d77b5e X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Sep 2020 15:46:13.6078 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: aFO/se0PZi+n6tM7ezMcLGj9MKtRZj3qprSfFF4dMPCjRpezLoD5yW5pBbsWWl18mxhmRFizo7ewym9l+oQQ/w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR02MB6850 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Rob, Thanks for the review. > -----Original Message----- > From: Rob Herring > Sent: Wednesday, September 9, 2020 4:35 AM > To: Manish Narani > Cc: gregkh@linuxfoundation.org; Michal Simek ; > balbi@kernel.org; p.zabel@pengutronix.de; linux-usb@vger.kernel.org; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org; git > Subject: Re: [PATCH 1/2] dt-bindings: usb: dwc3-xilinx: Add documentation= for > Versal DWC3 Controller >=20 > On Thu, Aug 27, 2020 at 12:14:00AM +0530, Manish Narani wrote: > > Add documentation for Versal DWC3 controller. Add required property > > 'reg' for the same. Also add optional properties for snps,dwc3. > > > > Signed-off-by: Manish Narani > > --- > > .../devicetree/bindings/usb/dwc3-xilinx.txt | 12 +++++++++++- > > 1 file changed, 11 insertions(+), 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt > b/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt > > index 4aae5b2cef56..dd41ed831411 100644 > > --- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt > > +++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt > > @@ -1,7 +1,8 @@ > > Xilinx SuperSpeed DWC3 USB SoC controller > > > > Required properties: > > -- compatible: Should contain "xlnx,zynqmp-dwc3" > > +- compatible: May contain "xlnx,zynqmp-dwc3" or "xlnx,versal- > dwc3" > > +- reg: Base address and length of the register control block > > - clocks: A list of phandles for the clocks listed in clock-names > > - clock-names: Should contain the following: > > "bus_clk" Master/Core clock, have to be >=3D 125 MHz for SS > > @@ -13,12 +14,19 @@ Required child node: > > A child node must exist to represent the core DWC3 IP block. The name = of > > the node is not important. The content of the node is defined in dwc3.= txt. > > > > +Optional properties for snps,dwc3: > > +- dma-coherent: Enable this flag if CCI is enabled in design. Adding t= his > > + flag configures Global SoC bus Configuration Register and > > + Xilinx USB 3.0 IP - USB coherency register to enable CCI. > > +- interrupt-names: This property provides the names of the interrupt i= ds > used >=20 > You have to define what the names are. 'dwc_usb3' seems pretty pointless > if only 1 name. OK. I am planning to add more interrupt ids going ahead. For now I will rem= ove this interrupt name in v2. The interrupt name will be added along with othe= r interrupt names. Thanks, Manish