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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: cadence.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5cdd18a9-7c90-4282-4944-08d5f94fec0a X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Aug 2018 14:46:39.8021 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: d36035c5-6ce6-4662-a3dc-e762e61ae4c9 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR07MB5189 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Kishon, > -----Original Message----- > From: Kishon Vijay Abraham I > Sent: 24 July 2018 04:57 > To: Scott Telford ; linux-kernel@vger.kernel.org; > linux-arm-kernel@lists.infradead.org; Damian Kos > Subject: Re: [PATCH v2] phy: Add driver for Cadence MHDP DisplayPort > SD0801 PHY >=20 [..] > > +static void cdns_dp_phy_pma_cmn_cfg_25mhz(struct cdns_dp_phy > *cdns_phy) > > +{ > > + /* refclock registers - assumes 25 MHz refclock */ > > + writel(0x0019, cdns_phy->sd_base + CMN_SSM_BIAS_TMR); > > + writel(0x0032, cdns_phy->sd_base + CMN_PLLSM0_PLLPRE_TMR); > > + writel(0x00D1, cdns_phy->sd_base + CMN_PLLSM0_PLLLOCK_TMR); > > + writel(0x0032, cdns_phy->sd_base + CMN_PLLSM1_PLLPRE_TMR); > > + writel(0x00D1, cdns_phy->sd_base + CMN_PLLSM1_PLLLOCK_TMR); > > + writel(0x007D, cdns_phy->sd_base + CMN_BGCAL_INIT_TMR); > > + writel(0x007D, cdns_phy->sd_base + CMN_BGCAL_ITER_TMR); > > + writel(0x0019, cdns_phy->sd_base + CMN_IBCAL_INIT_TMR); > > + writel(0x001E, cdns_phy->sd_base + CMN_TXPUCAL_INIT_TMR); > > + writel(0x0006, cdns_phy->sd_base + CMN_TXPUCAL_ITER_TMR); > > + writel(0x001E, cdns_phy->sd_base + CMN_TXPDCAL_INIT_TMR); > > + writel(0x0006, cdns_phy->sd_base + CMN_TXPDCAL_ITER_TMR); > > + writel(0x02EE, cdns_phy->sd_base + CMN_RXCAL_INIT_TMR); > > + writel(0x0006, cdns_phy->sd_base + CMN_RXCAL_ITER_TMR); > > + writel(0x0002, cdns_phy->sd_base + CMN_SD_CAL_INIT_TMR); > > + writel(0x0002, cdns_phy->sd_base + CMN_SD_CAL_ITER_TMR); > > + writel(0x000E, cdns_phy->sd_base + CMN_SD_CAL_REFTIM_START); > > + writel(0x012B, cdns_phy->sd_base + CMN_SD_CAL_PLLCNT_START); > > + /* PLL registers */ > > + writel(0x0409, cdns_phy->sd_base + > CMN_PDIAG_PLL0_CP_PADJ_M0); > > + writel(0x1001, cdns_phy->sd_base + > CMN_PDIAG_PLL0_CP_IADJ_M0); > > + writel(0x0F08, cdns_phy->sd_base + > CMN_PDIAG_PLL0_FILT_PADJ_M0); > > + writel(0x0004, cdns_phy->sd_base + CMN_PLL0_DSM_DIAG_M0); > > + writel(0x00FA, cdns_phy->sd_base + > CMN_PLL0_VCOCAL_INIT_TMR); > > + writel(0x0004, cdns_phy->sd_base + > CMN_PLL0_VCOCAL_ITER_TMR); > > + writel(0x00FA, cdns_phy->sd_base + > CMN_PLL1_VCOCAL_INIT_TMR); > > + writel(0x0004, cdns_phy->sd_base + > CMN_PLL1_VCOCAL_ITER_TMR); > > + writel(0x0318, cdns_phy->sd_base + > CMN_PLL0_VCOCAL_REFTIM_START); >=20 > Are these values that are written just calibration data or are they bitfi= elds > for a specific setting. If they are not calibration data, then macros sho= uld be > added.=20 These are calibration values. I will post a new revision addressing your other comments shortly. Regards, Scott.