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Fri, 17 Sep 2021 04:44:13 +0000 From: "Sanil, Shruthi" To: Rob Herring CC: "daniel.lezcano@linaro.org" , "tglx@linutronix.de" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "andriy.shevchenko@linux.intel.com" , "kris.pan@linux.intel.com" , "mgross@linux.intel.com" , "Thokala, Srikanth" , "Raja Subramanian, Lakshmi Bai" , "Sangannavar, Mallikarjunappa" Subject: RE: [PATCH v7 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer Thread-Topic: [PATCH v7 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer Thread-Index: AQHXqMfNL5OqpoLD/Em9Sy8AMwk1fKunGTIAgACSNjA= Date: Fri, 17 Sep 2021 04:44:13 +0000 Message-ID: References: <20210913174955.32330-1-shruthi.sanil@intel.com> <20210913174955.32330-2-shruthi.sanil@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.6.200.16 authentication-results: kernel.org; dkim=none (message not signed) header.d=none;kernel.org; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BYAPR11MB3128.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 85a31a69-6e23-4420-dc62-08d97995cc74 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Sep 2021 04:44:13.5395 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 9B7LOCuJNQuBDnLj5ap6RadPuwM2nZUuoOcklSSrw9Tz66FNZMstsgX0rCA6Vb7AmwA45nyFVg66VY0SaICmQw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR11MB4500 X-OriginatorOrg: intel.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Rob Herring > Sent: Friday, September 17, 2021 1:30 AM > To: Sanil, Shruthi > Cc: daniel.lezcano@linaro.org; tglx@linutronix.de; linux- > kernel@vger.kernel.org; devicetree@vger.kernel.org; > andriy.shevchenko@linux.intel.com; kris.pan@linux.intel.com; > mgross@linux.intel.com; Thokala, Srikanth ; > Raja Subramanian, Lakshmi Bai ; > Sangannavar, Mallikarjunappa > Subject: Re: [PATCH v7 1/2] dt-bindings: timer: Add bindings for Intel Ke= em > Bay SoC Timer >=20 > On Mon, Sep 13, 2021 at 11:19:54PM +0530, shruthi.sanil@intel.com wrote: > > From: Shruthi Sanil > > > > Add Device Tree bindings for the Timer IP, which can be used as > > clocksource and clockevent device in the Intel Keem Bay SoC. > > > > Reviewed-by: Andy Shevchenko > > Signed-off-by: Shruthi Sanil > > --- > > .../bindings/timer/intel,keembay-timer.yaml | 172 ++++++++++++++++++ > > 1 file changed, 172 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml > > b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml > > new file mode 100644 > > index 000000000000..80e7785845ac > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/timer/intel,keembay- > timer.yaml > > @@ -0,0 +1,172 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/timer/intel,keembay-timer.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Intel Keem Bay SoC Timers > > + > > +maintainers: > > + - Shruthi Sanil > > + > > +description: | > > + The Intel Keem Bay timer driver supports 1 free running counter and = 8 > timers. > > + Each timer is capable of generating inividual interrupt. > > + Both the features are enabled through the timer general config regis= ter. > > + > > + The parent node represents the common general configuration details > > + and the child nodes represents the counter and timers. > > + > > +properties: > > + compatible: > > + enum: > > + - simple-mfd >=20 > Removing is not the right solution. What you need is: >=20 > items: > - const: intel,keembay-gpt-creg > - const: simple-mfd >=20 Thank You Rob! I'll update accordingly and submit the patch. > > + > > + reg: > > + description: General configuration register address and length. > > + maxItems: 1 > > + > > + ranges: true > > + > > + "#address-cells": > > + const: 1 > > + > > + "#size-cells": > > + const: 1 > > + > > +required: > > + - compatible > > + - reg > > + - ranges > > + - "#address-cells" > > + - "#size-cells" > > + > > +patternProperties: > > + "^counter@[0-9a-f]+$": > > + type: object > > + description: Properties for Intel Keem Bay counter > > + > > + properties: > > + compatible: > > + enum: > > + - intel,keembay-counter > > + > > + reg: > > + maxItems: 1 > > + > > + clocks: > > + maxItems: 1 > > + > > + required: > > + - compatible > > + - reg > > + - clocks > > + > > + "^timer@[0-9a-f]+$": > > + type: object > > + description: Properties for Intel Keem Bay timer > > + > > + properties: > > + compatible: > > + enum: > > + - intel,keembay-timer > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + maxItems: 1 > > + > > + clocks: > > + maxItems: 1 > > + > > + required: > > + - compatible > > + - reg > > + - interrupts > > + - clocks > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include > > + #include > > + #define KEEM_BAY_A53_TIM > > + > > + soc { > > + #address-cells =3D <0x2>; > > + #size-cells =3D <0x2>; > > + > > + gpt@20331000 { > > + compatible =3D "simple-mfd"; > > + reg =3D <0x0 0x20331000 0x0 0xc>; > > + ranges =3D <0x0 0x0 0x20330000 0xF0>; > > + #address-cells =3D <0x1>; > > + #size-cells =3D <0x1>; > > + > > + counter@e8 { > > + compatible =3D "intel,keembay-counter"; > > + reg =3D <0xe8 0x8>; > > + clocks =3D <&scmi_clk KEEM_BAY_A53_TIM>; > > + }; > > + > > + timer@10 { > > + compatible =3D "intel,keembay-timer"; > > + reg =3D <0x10 0xc>; > > + interrupts =3D ; > > + clocks =3D <&scmi_clk KEEM_BAY_A53_TIM>; > > + }; > > + > > + timer@20 { > > + compatible =3D "intel,keembay-timer"; > > + reg =3D <0x20 0xc>; > > + interrupts =3D ; > > + clocks =3D <&scmi_clk KEEM_BAY_A53_TIM>; > > + }; > > + > > + timer@30 { > > + compatible =3D "intel,keembay-timer"; > > + reg =3D <0x30 0xc>; > > + interrupts =3D ; > > + clocks =3D <&scmi_clk KEEM_BAY_A53_TIM>; > > + }; > > + > > + timer@40 { > > + compatible =3D "intel,keembay-timer"; > > + reg =3D <0x40 0xc>; > > + interrupts =3D ; > > + clocks =3D <&scmi_clk KEEM_BAY_A53_TIM>; > > + }; > > + > > + timer@50 { > > + compatible =3D "intel,keembay-timer"; > > + reg =3D <0x50 0xc>; > > + interrupts =3D ; > > + clocks =3D <&scmi_clk KEEM_BAY_A53_TIM>; > > + }; > > + > > + timer@60 { > > + compatible =3D "intel,keembay-timer"; > > + reg =3D <0x60 0xc>; > > + interrupts =3D ; > > + clocks =3D <&scmi_clk KEEM_BAY_A53_TIM>; > > + }; > > + > > + timer@70 { > > + compatible =3D "intel,keembay-timer"; > > + reg =3D <0x70 0xc>; > > + interrupts =3D ; > > + clocks =3D <&scmi_clk KEEM_BAY_A53_TIM>; > > + }; > > + > > + timer@80 { > > + compatible =3D "intel,keembay-timer"; > > + reg =3D <0x80 0xc>; > > + interrupts =3D ; > > + clocks =3D <&scmi_clk KEEM_BAY_A53_TIM>; > > + }; > > + }; > > + }; > > + > > +... > > -- > > 2.17.1 > > > >