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Tue, 13 Aug 2024 22:24:52 +0000 From: To: CC: , , , , , , , , , , , , , , Subject: RE: [PATCH net-next 3/4] net: dsa: microchip: handle most interrupts in KSZ9477/KSZ9893 switch families Thread-Topic: [PATCH net-next 3/4] net: dsa: microchip: handle most interrupts in KSZ9477/KSZ9893 switch families Thread-Index: AQHa6rVcFRrm35N53kCqztaSs7g9LbIgxFsAgAUE27A= Date: Tue, 13 Aug 2024 22:24:52 +0000 Message-ID: References: <20240809233840.59953-1-Tristram.Ha@microchip.com> <20240809233840.59953-4-Tristram.Ha@microchip.com> <301c5f90-0307-4c23-b867-6677d41dce47@lunn.ch> In-Reply-To: <301c5f90-0307-4c23-b867-6677d41dce47@lunn.ch> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=microchip.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: BYAPR11MB3558:EE_|SA1PR11MB6805:EE_ x-ms-office365-filtering-correlation-id: 1e77b791-c865-4422-f11e-08dcbbe6c06c x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:BYAPR11MB3558.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(1800799024)(7416014)(366016)(38070700018);DIR:OUT;SFP:1101; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BYAPR11MB3558.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1e77b791-c865-4422-f11e-08dcbbe6c06c X-MS-Exchange-CrossTenant-originalarrivaltime: 13 Aug 2024 22:24:52.4909 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: X3DxBoPk3FuGePy5puCpZ9nBMZbKEOQmm4dmorBX5TZXO8r+0hcYIc2DZ8iFNidV4sIxSvxk5tsjLLSQjWzYDNQG37S+UiXLOiyDZpojmug= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR11MB6805 > > +static irqreturn_t ksz9477_handle_port_irq(struct ksz_device *dev, u8 = port, > > + u8 *data) > > +{ > > + struct dsa_switch *ds =3D dev->ds; > > + struct phy_device *phydev; > > + int cnt =3D 0; > > + > > + phydev =3D mdiobus_get_phy(ds->user_mii_bus, port); > > + if (*data & PORT_PHY_INT) { > > + /* Handle the interrupt if there is no PHY device or its > > + * interrupt is not registered yet. > > + */ > > + if (!phydev || phydev->interrupts !=3D PHY_INTERRUPT_ENAB= LED) { > > + u8 phy_status; > > + > > + ksz_pread8(dev, port, REG_PORT_PHY_INT_STATUS, > > + &phy_status); > > + if (phydev) > > + phy_trigger_machine(phydev); > > + ++cnt; > > + *data &=3D ~PORT_PHY_INT; > > + } > > + } >=20 > This looks like a layering violation. Why is this needed? An interrupt > controller generally has no idea what the individual interrupt is > about. It just calls into the interrupt core to get the handler > called, and then clears the interrupt. Why does that not work here? >=20 > What other DSA drivers do if they need to handle some of the > interrupts is just request the interrupt like any other driver: >=20 > https://elixir.bootlin.com/linux/v6.10.3/source/drivers/net/dsa/mv88e6xxx= /pcs- > 639x.c#L95 The PHY and ACL interrupt handling can be removed, but the SGMII interrupt handling cannot as the SGMII port is simulated as having an internal PHY but the regular PHY interrupt processing will not clear the interrupt. Furthermore, there will be a situation where the SGMII interrupt is triggered before the PHY interrupt handling function is registered.