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Wed, 21 Apr 2021 05:25:52 +0000 From: "Wu, Hao" To: "matthew.gerlach@linux.intel.com" , "trix@redhat.com" , "linux-fpga@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "Xu, Yilun" , "Weight, Russell H" , "mdf@kernel.org" Subject: RE: [PATCH] fpga: dfl: pci: gracefully handle misconfigured port entries Thread-Topic: [PATCH] fpga: dfl: pci: gracefully handle misconfigured port entries Thread-Index: AQHXNgpK6sZ5wt8PgU2xWx05XVpyOqq+btGQ Date: Wed, 21 Apr 2021 05:25:52 +0000 Message-ID: References: <20210420172740.707259-1-matthew.gerlach@linux.intel.com> In-Reply-To: <20210420172740.707259-1-matthew.gerlach@linux.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 authentication-results: linux.intel.com; dkim=none (message not signed) header.d=none;linux.intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [192.102.204.53] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 0b404b63-ee05-4123-62d1-08d90485ee7e x-ms-traffictypediagnostic: BY5PR11MB4273: x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:238; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BYAPR11MB3816.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0b404b63-ee05-4123-62d1-08d90485ee7e X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Apr 2021 05:25:52.6458 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 97YFTA7quXmaQPYVDCUSr8da3dmVSxLSft/oQNAhSepbuiNw388Na7OKABLRecZpyI1zJG5jTfA47rM3PR3BXw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR11MB4273 X-OriginatorOrg: intel.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > Subject: [PATCH] fpga: dfl: pci: gracefully handle misconfigured port ent= ries >=20 > From: Matthew Gerlach >=20 > Gracefully ignore misconfigured port entries encountered in > incorrect FPGA images. >=20 > Signed-off-by: Matthew Gerlach > --- > drivers/fpga/dfl-pci.c | 16 +++++++++++++++- > 1 file changed, 15 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c > index b44523e..660d3b6 100644 > --- a/drivers/fpga/dfl-pci.c > +++ b/drivers/fpga/dfl-pci.c > @@ -212,6 +212,7 @@ static int find_dfls_by_default(struct pci_dev *pcide= v, > int port_num, bar, i, ret =3D 0; > resource_size_t start, len; > void __iomem *base; > + int bars =3D 0; > u32 offset; > u64 v; >=20 > @@ -228,6 +229,7 @@ static int find_dfls_by_default(struct pci_dev *pcide= v, > if (dfl_feature_is_fme(base)) { > start =3D pci_resource_start(pcidev, 0); > len =3D pci_resource_len(pcidev, 0); > + bars |=3D BIT(0); >=20 > dfl_fpga_enum_info_add_dfl(info, start, len); >=20 > @@ -253,9 +255,21 @@ static int find_dfls_by_default(struct pci_dev *pcid= ev, > */ > bar =3D FIELD_GET(FME_PORT_OFST_BAR_ID, v); > offset =3D FIELD_GET(FME_PORT_OFST_DFH_OFST, v); > + if (bars & BIT(bar)) { > + dev_warn(&pcidev->dev, "skipping bad port > BAR %d\n", bar); > + continue; > + } Will it be a real problem that multiple ports are inside one BAR but differ= ent offsets? Hao > + > start =3D pci_resource_start(pcidev, bar) + offset; > - len =3D pci_resource_len(pcidev, bar) - offset; > + len =3D pci_resource_len(pcidev, bar); > + if (offset >=3D len) { > + dev_warn(&pcidev->dev, "bad port > offset %u >=3D %pa\n", > + offset, &len); > + continue; > + } >=20 > + len -=3D offset; > + bars |=3D BIT(bar); > dfl_fpga_enum_info_add_dfl(info, start, len); > } > } else if (dfl_feature_is_port(base)) { > -- > 1.8.3.1