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Mon, 11 Feb 2019 16:23:37 +0000 Received: from BYAPR12MB3398.namprd12.prod.outlook.com ([fe80::5c0f:3413:bd4c:3dd3]) by BYAPR12MB3398.namprd12.prod.outlook.com ([fe80::5c0f:3413:bd4c:3dd3%5]) with mapi id 15.20.1601.023; Mon, 11 Feb 2019 16:23:37 +0000 From: Sowjanya Komatineni To: Wolfram Sang CC: "thierry.reding@gmail.com" , Jonathan Hunter , Mantravadi Karthik , "Shardar Mohammed" , Timo Alho , "peda@axentia.se" , "digetx@gmail.com" , "linux-tegra@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-i2c@vger.kernel.org" Subject: RE: [PATCH V18 6/6] i2c: tegra: add i2c interface timing support Thread-Topic: [PATCH V18 6/6] i2c: tegra: add i2c interface timing support Thread-Index: AQHUv+CHS8iiD7Agv0Wp9axF0O15H6XalJQAgAA0TeA= Date: Mon, 11 Feb 2019 16:23:37 +0000 Message-ID: References: <1549652382-5476-1-git-send-email-skomatineni@nvidia.com> <1549652382-5476-6-git-send-email-skomatineni@nvidia.com> <20190211130322.2kpoky3scnqnxulw@ninjato> In-Reply-To: <20190211130322.2kpoky3scnqnxulw@ninjato> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=skomatineni@nvidia.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1549902223; bh=TyJxQ37NfELI1jRm5UbbuCIv5rxYrbxE5inlI/NNqQQ=; h=X-PGP-Universal:From:To:CC:Subject:Thread-Topic:Thread-Index:Date: Message-ID:References:In-Reply-To:Accept-Language:X-MS-Has-Attach: X-MS-TNEF-Correlator:authentication-results:x-originating-ip: x-ms-publictraffictype:x-microsoft-exchange-diagnostics: x-ms-office365-filtering-correlation-id:x-microsoft-antispam: x-ms-traffictypediagnostic:x-microsoft-antispam-prvs: x-forefront-prvs:x-forefront-antispam-report:received-spf: x-ms-exchange-senderadcheck:x-microsoft-antispam-message-info: MIME-Version:X-MS-Exchange-CrossTenant-Network-Message-Id: X-MS-Exchange-CrossTenant-originalarrivaltime: X-MS-Exchange-CrossTenant-fromentityheader: X-MS-Exchange-CrossTenant-id:X-MS-Exchange-CrossTenant-mailboxtype: X-MS-Exchange-Transport-CrossTenantHeadersStamped:X-OriginatorOrg: Content-Language:Content-Type:Content-Transfer-Encoding; b=KEeWnknnqqfuK7nPvNscDyYvN2i5L1KxYbxN/Nsjkywp1ILLFrBRH8+UpB5dqe+Nz jm2j7/YFlKrWdX3ItTj+AU6MKCwacIXv8UfCpsOhmiIKCy5etdMFbPSjfLbFoA2MJJ k79wLW05Z/VpBywhNvqWAFooVjzvjrSua6ssPNUzkaCR+y+vrGp/AYoa+TCRH4n54u 36ackSGM3zIJLr/jEYbajNKe03vu61V/Gg8wn7+dzNSpjrXglJXmlwwru46LDNB2ln JayMthqkCYcxA2SHVwtjlxFc6qv9UuqBw09yc8Tw3Fl4Zxrn0HuW5oWPdyE50y0Drn i2y7RnuZ3yuKg== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > On Fri, Feb 08, 2019 at 10:59:42AM -0800, Sowjanya Komatineni wrote: > > This patch adds I2C interface timing registers support for proper bus=20 > > rate configuration along with meeting the I2C spec setup and hold=20 > > times based on the tuning performed on Tegra210, > > Tegra186 and Tegra194 platforms. > >=20 > > I2C_INTERFACE_TIMING_0 register contains TLOW and THIGH field and=20 > > Tegra I2C controller design uses them as a part of internal clock=20 > > divisor. > >=20 > > I2C_INTERFACE_TIMING_1 register contains the setup and hold times for=20 > > start and stop conditions. > >=20 > > Acked-by: Thierry Reding > > Reviewed-by: Dmitry Osipenko > > Tested-by: Dmitry Osipenko > > Signed-off-by: Sowjanya Komatineni > > Are you aware that we also have DT bindings for various I2C timing values= ? They are usually board dependent and not so much SoC dependent. > Please check here: > > Documentation/devicetree/bindings/i2c/i2c.txt > > (Oops, I noticed 'i2c-sda-hold-time-ns' is missing from the docs. Will fi= x that ASAP) > > Just saying. The patch here is fine for me. DT support could be added lat= er, if you want that. > Hi Wolfram, Yes I looked into those and the reason I added them as part of hw_feature i= nside driver are 1. property is in-terms of ns for fall time but the value we program in int= erface timing is not exact ns time 2. Below are the timing parameters need to be programmed for tegra I2C and = I don't see equivalent property for each of those TSU_STA : Setup time for repeated START condition THD_STA : Hold time for (repeated) START condition TSU_STO : Setup time for STOP condition TBUF: Bus free time b/w STOP and START conditions 3. All above Timing configuration settings are different for different spee= d modes (STD/FM & FM+/HS Mode)=20 4. All tegra platforms of specific Tegra chip has the same timing configura= tion at-least for now so added this info as part of hw feature inside the d= river. Sowjanya