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Add a DTSI file for it. Signed-off-by: Icenowy Zheng --- .../arm64/boot/dts/allwinner/sun50i-r329.dtsi | 275 ++++++++++++++++++ 1 file changed, 275 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-r329.dtsi diff --git a/arch/arm64/boot/dts/allwinner/sun50i-r329.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-r329.dtsi new file mode 100644 index 000000000000..249ed9ff0c5c --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-r329.dtsi @@ -0,0 +1,275 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2021 Sipeed + +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <1>; + enable-method = "psci"; + }; + }; + + osc24M: osc24M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + arm,no-tick-in-suspend; + interrupts = , + , + , + ; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + watchdog: watchdog@20000a0 { + compatible = "allwinner,sun50i-r329-wdt-reset", + "allwinner,sun50i-r329-wdt", + "allwinner,sun6i-a31-wdt"; + reg = <0x020000a0 0x20>; + interrupts = ; + clocks = <&osc24M>; + }; + + pio: pinctrl@2000400 { + compatible = "allwinner,sun50i-r329-pinctrl"; + reg = <0x02000400 0x400>; + interrupts = , + , + , + ; + clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + + uart0_pb_pins: uart0-pb-pins { + pins = "PB4", "PB5"; + function = "uart0"; + }; + + mmc0_pf_pins: mmc0-pf-pins { + pins = "PF0", "PF1", "PF2", + "PF3", "PF4", "PF5"; + function = "mmc0"; + }; + + mmc1_clk_pg0: mmc1-clk-pg0 { + pins = "PG0"; + function = "mmc1_clk"; + }; + + mmc1_cmd_pg1: mmc1-clk-pg1 { + pins = "PG1"; + function = "mmc1_cmd"; + }; + + mmc1_d0_pg2: mmc1-clk-pg2 { + pins = "PG2"; + function = "mmc1_d0"; + }; + + mmc1_d1_pg3: mmc1-clk-pg3 { + pins = "PG3"; + function = "mmc1_d1"; + }; + + mmc1_d2_pg4: mmc1-clk-pg4 { + pins = "PG4"; + function = "mmc1_d2"; + }; + + mmc1_d3_pg5: mmc1-clk-pg5 { + pins = "PG5"; + function = "mmc1_d3"; + }; + }; + + ccu: clock@2001000 { + compatible = "allwinner,sun50i-r329-ccu"; + reg = <0x02001000 0x1000>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, + <&r_ccu CLK_PLL_CPUX>, + <&r_ccu CLK_PLL_PERIPH>, + <&r_ccu CLK_PLL_PERIPH_2X>, + <&r_ccu CLK_PLL_PERIPH_800M>, + <&r_ccu CLK_PLL_AUDIO0>, + <&r_ccu CLK_PLL_AUDIO0_DIV2>, + <&r_ccu CLK_PLL_AUDIO0_DIV5>, + <&r_ccu CLK_PLL_AUDIO1>, + <&r_ccu CLK_PLL_AUDIO1_2X>, + <&r_ccu CLK_PLL_AUDIO1_4X>; + clock-names = "hosc", "losc", "iosc", + "pll-cpux", + "pll-periph", + "pll-periph-2x", + "pll-periph-800m", + "pll-audio0", + "pll-audio0-div2", + "pll-audio0-div5", + "pll-audio1", + "pll-audio1-2x", + "pll-audio1-4x"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + uart0: serial@2500000 { + compatible = "snps,dw-apb-uart"; + reg = <0x02500000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; + status = "disabled"; + }; + + uart1: serial@2500400 { + compatible = "snps,dw-apb-uart"; + reg = <0x02500400 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + status = "disabled"; + }; + + uart2: serial@2500800 { + compatible = "snps,dw-apb-uart"; + reg = <0x02500800 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + status = "disabled"; + }; + + uart3: serial@2500c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x02500c00 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; + status = "disabled"; + }; + + gic: interrupt-controller@3021000 { + compatible = "arm,gic-400"; + reg = <0x03021000 0x1000>, + <0x03022000 0x2000>, + <0x03024000 0x2000>, + <0x03026000 0x2000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + + mmc0: mmc@4020000 { + compatible = "allwinner,sun50i-r329-mmc"; + reg = <0x04020000 0x1000>; + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + interrupts = ; + max-frequency = <150000000>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@4021000 { + compatible = "allwinner,sun50i-r329-mmc"; + reg = <0x04021000 0x1000>; + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC1>; + reset-names = "ahb"; + interrupts = ; + max-frequency = <150000000>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + r_ccu: clock@7010000 { + compatible = "allwinner,sun50i-r329-r-ccu"; + reg = <0x07010000 0x10000>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>; + clock-names = "hosc", "losc", "iosc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + r_pio: pinctrl@7022000 { + compatible = "allwinner,sun50i-r329-r-pinctrl"; + reg = <0x07022000 0x400>; + interrupts = , + , + ; + clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc CLK_OSC32K>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + rtc: rtc@7090000 { + compatible = "allwinner,sun50i-r329-rtc"; + reg = <0x07090000 0x400>; + interrupts = ; + clocks = <&r_ccu CLK_R_BUS_RTC>, <&osc24M>, <&r_ccu CLK_R_AHB>; + clock-names = "bus", "hosc", "ahb"; + #clock-cells = <1>; + }; + }; +}; -- 2.35.1