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Mon, 12 Nov 2018 16:57:55 -0800 (PST) Received: from us01wembx1.internal.synopsys.com ([169.254.1.228]) by us01wehtc1.internal.synopsys.com ([::1]) with mapi id 14.03.0415.000; Mon, 12 Nov 2018 16:57:55 -0800 From: Vineet Gupta To: Florian Fainelli , "linux-kernel@vger.kernel.org" CC: Catalin Marinas , Will Deacon , Rob Herring , Frank Rowand , Andrew Morton , "Marc Zyngier" , Russell King , Andrey Ryabinin , Andrey Konovalov , Masahiro Yamada , Robin Murphy , Laura Abbott , Stefan Agner , Johannes Weiner , "Greg Hackmann" , Kristina Martsenko , CHANDAN VN , "moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE" , "rppt@linux.ibm.com" , "linux@armlinux.org.uk" , "green.hu@gmail.com" , "deanbo422@gmail.com" , "gxt@pku.edu.cn" , "ard.biesheuvel@linaro.org" , "linux-snps-arc@lists.infradead.org" Subject: Re: [PATCH v4 6/6] arch: Move initrd= parsing into do_mounts_initrd.c Thread-Topic: [PATCH v4 6/6] arch: Move initrd= parsing into do_mounts_initrd.c Thread-Index: AQHUdVsG6LD9rqw+mkiEXoDtFpj/vg== Date: Tue, 13 Nov 2018 00:57:54 +0000 Message-ID: References: <20181105225431.24485-1-f.fainelli@gmail.com> <20181105225431.24485-7-f.fainelli@gmail.com> <05f56763-1530-933d-2ce3-3653ad4c685f@gmail.com> <04d6d0cb-8e60-88a0-061e-62c7c70024c5@gmail.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.144.199.104] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/12/18 4:52 PM, Florian Fainelli wrote:=0A= > On 11/12/18 4:40 PM, Vineet Gupta wrote:=0A= >> On 11/12/18 4:38 PM, Florian Fainelli wrote:=0A= >>>>> #ifdef CONFIG_BLK_DEV_INITRD=0A= >>>>> - if (initrd_start)=0A= >>>>> - memblock_reserve(__pa(initrd_start), initrd_end - initrd_start);= =0A= >>>>> + if (phys_initrd_size) {=0A= >>>>> + memblock_reserve(phys_initrd_start, phys_initrd_size);=0A= >>>>> + initrd_start =3D (unsigned long)__va(phys_initrd_start);=0A= >>>>> + initrd_end =3D initrd_start + phys_initrd_size;=0A= >>>>> + }=0A= >>>>> #endif=0A= >>>> The common code now uses phys_initrd*, and you also use the same in AR= C code, do=0A= >>>> we still need the initrd_* setting here ?=0A= >>>> ARC semantics was using them as PA anyways.=0A= >>> Yes, the generic initrd code expects initrd_start/end to be virtual=0A= >>> addresses, which we now directly derive from phys_initrd_start, that=0A= >>> should really be equivalent.=0A= >> So we can skip this explicit setting above - ARC arch code doesn't acces= s the virt=0A= >> initrd_start=0A= > OK, you are saying we could just have the generic initrd code do this=0A= > assignment instead of having each architecture do it, is that a correct= =0A= > understanding? =0A= =0A= Correct !=0A= =0A= > If so, I suppose it could be done, whether as of this=0A= > patch series or as a follow-up, either way is fine with me.=0A= =0A= If it is not too much trouble, I'd prefer this now. I should have chimed ea= rlier.=0A= =0A= > One possible caveat is if __va() and __phys_to_virt() behave differently= =0A= > (e.g: because of CONFIG_DEBUG_VIRTUAL or other things).=0A= =0A= =0A= Thing is, after your patches, we don't use the vanilla initrd_xxx in arch c= ode any=0A= longer. So this becomes just an implementation detail, which core code may = or=0A= maynot need and if it does, this needs to work already w/o having to set an= ything=0A= in arch code. Agree ?=0A= =0A= Thx,=0A= -Vineet=0A=