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[209.85.222.174]) by smtp.gmail.com with ESMTPSA id az6sm11434052qkb.70.2021.09.20.10.55.02 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 20 Sep 2021 10:55:02 -0700 (PDT) Received: by mail-qk1-f174.google.com with SMTP id 72so33648586qkk.7 for ; Mon, 20 Sep 2021 10:55:02 -0700 (PDT) X-Received: by 2002:a9d:7483:: with SMTP id t3mr21162684otk.3.1632160112361; Mon, 20 Sep 2021 10:48:32 -0700 (PDT) MIME-Version: 1.0 References: <20210830123704.221494-1-verdre@v0yd.nl> <20210830123704.221494-2-verdre@v0yd.nl> <0ce93e7c-b041-d322-90cd-40ff5e0e8ef0@v0yd.nl> In-Reply-To: <0ce93e7c-b041-d322-90cd-40ff5e0e8ef0@v0yd.nl> From: Brian Norris Date: Mon, 20 Sep 2021 10:48:21 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 1/2] mwifiex: Use non-posted PCI register writes To: =?UTF-8?Q?Jonas_Dre=C3=9Fler?= Cc: Andy Shevchenko , Amitkumar Karwar , Ganapathi Bhat , Xinming Hu , Kalle Valo , "David S. Miller" , Jakub Kicinski , Tsuchiya Yuto , linux-wireless , "" , Linux Kernel , linux-pci , Maximilian Luz , Andy Shevchenko , Bjorn Helgaas , =?UTF-8?Q?Pali_Roh=C3=A1r?= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, Sep 18, 2021 at 12:37 AM Jonas Dre=C3=9Fler wrote: > Thanks for the pointer to that commit Brian, it turns out this is > actually the change that causes the "Firmware wakeup failed" issues that > I'm trying to fix with the second patch here. Huh. That's interesting, although I guess it makes some sense given your theory of "dropped writes". FWIW, this strategy (post a single write, then wait for wakeup) is the same used by some other chips/drivers too (e.g., ath10k/pci), although in those cases card wakeup is much much faster. But if the bus was dropping writes somehow, those strategies would fail too. > Also my approach is a lot messier than just reverting > 062e008a6e83e7c4da7df0a9c6aefdbc849e2bb3 and also appears to be blocking > even longer... For the record, in case you're talking about my data ("blocking even longer"): I was only testing patch 1. Patch 2 isn't really relevant to my particular systems (Rockchip RK3399 + Marvell 8997/PCIe), because (a) I'm pretty sure my system isn't "dropping" any reads or writes (b) all my delay is in the read-back; the Rockchip PCIe bus is waiting indefinitely for the card to wake up, instead of timing out and reporting all-1's like many x86 systems appear to do (I've tested this). So, the 6ms delay is entirely sitting in the ioread32(), not a delay loop. I haven't yet tried your version 2 (which avoids the blocking read to wake up; good!), but it sounds like in theory it could solve your problem while avoiding 6ms delays for me. I intend to test your v2 this week. > Does anyone have an idea what could be the reason for the posted write > not going through, or could that also be a potential firmware bug in the > chip? I have no clue about that. That does sound downright horrible, but so are many things when dealing with this family of hardware/firmware. I'm not sure how to prove out whether this is a host bus problem, or an endpoint/firmware problem, other than perhaps trying the same module/firmware on another system, if that's possible. Anyway, to reiterate: I'm not fundamentally opposed to v2 (pending a test run here), even if it is a bit ugly and perhaps not 100% understood. Brian