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AJvYcCUi4WNRnTH/bSS/z0kV0idAgoBmh9MO0Twd2l1GneJDRaRI7TweVsLGO6Y5zanAmA2DwwS/1JueriPinJE=@vger.kernel.org X-Gm-Message-State: AOJu0Yxs/6+zoTlW5vZCL+IEGt82TQMakSEs5CL98baJ0gqNd12XxLoA 7LRrjKGLovGHoAzWLBEj59ZWsKTpDlDOrSbsKTjAEgCxqG2gprVt2z3uWbXj3KNpkahcN53mLYu g2oBV/Uu8e444pPQPMullUWDBjviSW9E= X-Gm-Gg: ASbGncvpAxluMNoNRoZnkxwI8/FB+YJlB0sILPnXnlg7rXy9g3oa/9FrJoho+09nWB1 Lusto9MdNs16ourOxFsR07p5Cwm86FLIK6LwYBEeeqIk9r/k5xRKViGFfhmr0yl0HXm9CveXoPY IFu46x5N6ZNrfPAUP/Shx3dtECz80rchIp3laUs7Vgl3aZZDxAnieBccBQ6C9uujwwoljnrHegt Mg4P3ETdE5MqwdULLjDxekeyvHTbOHi X-Google-Smtp-Source: AGHT+IFHnGmRHmJr+YpPGsnnoZoqfJyt9jk/+n5kLjP1CHOy6XhDxWRnAYIfrfCsIi4lEcHTSz6IGQr7yPIPxN5B9f4= X-Received: by 2002:a05:600c:1f96:b0:46e:27f7:80ce with SMTP id 5b1f17b1804b1-46e612be465mr23677905e9.23.1759310970863; Wed, 01 Oct 2025 02:29:30 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250903161718.180488-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20250903161718.180488-3-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: "Lad, Prabhakar" Date: Wed, 1 Oct 2025 10:29:03 +0100 X-Gm-Features: AS18NWBlqD2UHra31fOQuHsSKmsMOeniTxCTqefAG_2I-HhVlcZOHoipA4udDNA Message-ID: Subject: Re: [PATCH v8 2/6] clk: renesas: rzv2h-cpg: Add support for DSI clocks To: Geert Uytterhoeven Cc: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Tomi Valkeinen , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Biju Das , Magnus Damm , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Fabrizio Castro , Tommaso Merciai , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Geert, Thank you for the review. On Wed, Sep 24, 2025 at 2:05=E2=80=AFPM Geert Uytterhoeven wrote: > > Hi Prabhakar, > > On Wed, 3 Sept 2025 at 18:17, Prabhakar wrot= e: > > From: Lad Prabhakar > > > > Add support for PLLDSI and PLLDSI divider clocks. > > > > Introduce the `renesas-rzv2h-cpg-pll.h` header to centralize and share > > PLLDSI related data structures, limits, and algorithms between the > > RZ/V2H(P) CPG and DSI drivers. > > > > The DSI PLL is functionally similar to the CPG's PLLDSI, but has slight= ly > > different parameter limits and omits the programmable divider present i= n > > CPG. To ensure precise frequency calculations, especially for milliHz-l= evel > > accuracy needed by the DSI driver, the shared algorithm allows both dri= vers > > to compute PLL parameters consistently using the same logic and input > > clock. > > > > Co-developed-by: Fabrizio Castro > > Signed-off-by: Fabrizio Castro > > Signed-off-by: Lad Prabhakar > > Reviewed-by: Biju Das > > Reviewed-by: Geert Uytterhoeven > > > --- a/drivers/clk/renesas/rzv2h-cpg.c > > +++ b/drivers/clk/renesas/rzv2h-cpg.c > > > +static int rzv2h_cpg_plldsi_div_determine_rate(struct clk_hw *hw, > > + struct clk_rate_request = *req) > > +{ > > + struct rzv2h_plldsi_div_clk *dsi_div =3D to_plldsi_div_clk(hw); > > + struct pll_clk *pll_clk =3D to_pll(clk_hw_get_parent(hw)); > > + struct rzv2h_cpg_priv *priv =3D dsi_div->priv; > > + struct rzv2h_pll_div_pars *dsi_params; > > + struct rzv2h_pll_dsi_info *dsi_info; > > + u64 rate_millihz; > > + > > + dsi_info =3D &priv->pll_dsi_info[pll_clk->pll.instance]; > > + dsi_params =3D &dsi_info->pll_dsi_parameters; > > + > > + rate_millihz =3D mul_u32_u32(req->rate, MILLI); > > + if (rate_millihz =3D=3D dsi_params->div.error_millihz + dsi_par= ams->div.freq_millihz) > > + goto exit_determine_rate; > > + > > + if (!rzv2h_get_pll_dtable_pars(dsi_info->pll_dsi_limits, dsi_pa= rams, dsi_div->dtable, > > + rate_millihz)) { > > + dev_err(priv->dev, > > + "failed to determine rate for req->rate: %lu\n"= , > > + req->rate); > > + return -EINVAL; > > + } > > + > > +exit_determine_rate: > > + req->rate =3D DIV_ROUND_CLOSEST_ULL(dsi_params->div.freq_millih= z, MILLI); > > + req->best_parent_rate =3D req->rate * dsi_params->div.divider_v= alue; > > + dsi_info->req_pll_dsi_rate =3D req->best_parent_rate; > > + > > + return 0; > > +}; > > Unneeded semicolon (there are three more below). I will fix that. Cheers, Prabhakar