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Peter Anvin" , Kees Cook , alyssa.milburn@intel.com, scott.d.constable@intel.com, Joao Moreira , Andrew Cooper , Sami Tolvanen , Nathan Chancellor , Masami Hiramatsu , ojeda@kernel.org, LKML Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Aug 14, 2025 at 2:17=E2=80=AFPM Peter Zijlstra wrote: > > Hi! > > A while ago FineIBT started using the instruction 0xEA to generate #UD. > All existing parts will generate #UD in 64bit mode on that instruction. > > However; Intel/AMD have not blessed using this instruction, it is on > their 'reserved' list for future use. > > Peter Anvin worked the committees and got use of 0xD6 blessed, and it > will be called UDB (per the next SDM or so). > > Reworking the FineIBT code to use UDB wasn't entirely trivial, and I've > had to switch the hash register to EAX in order to free up some bytes. > > Per the x86_64 ABI, EAX is used to pass the number of vector registers > for varargs -- something that should not happen in the kernel. More so, > we build with -mskip-rax-setup, which should leave EAX completely unused > in the calling convention. rax is used to pass tail_call count. See diagram in commit log: https://lore.kernel.org/all/20240714123902.32305-2-hffilwlqm@gmail.com/ Before that commit rax was used differently. Bottom line rax was used for a long time to support bpf_tail_calls. I'm traveling atm. So cc-ing folks for follow ups.