From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4FA6F3D76 for ; Sun, 22 Mar 2026 12:48:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774183725; cv=none; b=iffftkMR07rmB6vtGqGnQ6pwMoHwfaUWEDjQnomhx4zGZRz6J3mpz9CFuyvE9Lq5OSz4tnZgDkmnUzdVHVQAk0VwtguM9SGr7Mxm0Ylpwl3WiJ+nOToypzjTbKyGADjuB+OwJCEs0zW9VRwEX31UO3taVwZsY0i9DkGKruV8nHU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774183725; c=relaxed/simple; bh=+DtQACtjWQV/63LCvj8FhHvvOYsYlPtKyxT/kV73eXo=; h=MIME-Version:References:In-Reply-To:From:Date:Message-ID:Subject: To:Cc:Content-Type; b=REibEroG9Q7EzgD7MlL86o/G3iN7qMr5ynr44uMijh52kOLMLm9UGWQGYPxnhundwCiwyPiNAPPU5W6NpoUzunl/E0kSVRBkEesWOuhuQe2UCcfbjPQHOPw1UQVKlx5tgS7Jn//ZAppyoXE28veApQFrka3hOQE5km+hA86YABU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KEazxW4p; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KEazxW4p" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DBEBDC2BCC4 for ; Sun, 22 Mar 2026 12:48:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774183724; bh=+DtQACtjWQV/63LCvj8FhHvvOYsYlPtKyxT/kV73eXo=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=KEazxW4pdXQkm5fA4QYCeDVSQSUyoQbVBgva9d+VcWoLuR9yLkrFgiIhiTK8/5izU xpL4MQ7tWsi8tRzw9F/F9gA8dp7XDjLuuZi8mieg79pIeyky1vDyRP43ZmUzY0Zqrf n4LzlNcyy9i+oSoov4HVmLXKGhyCuA1UNLZL7sqjif7dQg8NeV54UgQnMd0+xGPiZG MjJ4kqhungFGye5yRLw0y3Tkd7kJgZXugDeITeHcDwOlnv0G42mtI8p34X5jY7vZqa pfQV2o/zLJcm9chzDBlcazV1OSFbbCVsrZ1j6PdwcqeyRi9e+1VXPsekAqDF8vPY6q EjM8ivRtQSy8A== Received: by mail-dl1-f49.google.com with SMTP id a92af1059eb24-126ea4b77adso3180893c88.1 for ; Sun, 22 Mar 2026 05:48:44 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCUT2NIU4ArSYjdiPu5NaZ8hcACWvdD4nYD6te7ms18Hus2PBoCFbKF2zUidF13+tZOJsulEOZov84U6TUI=@vger.kernel.org X-Gm-Message-State: AOJu0YzhxqLKcevOk/m2LfZwPXBTNywj6j2xyKwJkqbDQ0K9Fl5vOol/ dnv/FebqKYPd/xHxU/zXn92+9k2ZychOXasg/92xGtAVC4cS+0OI8BdHg4AiwhtVMXZ0KKYC41M 2msEpTziz3B6vKRLYhmploTAyd5TmpA== X-Received: by 2002:a05:7022:b85:b0:128:d786:8ac8 with SMTP id a92af1059eb24-12a725b332fmr3592564c88.0.1774183724047; Sun, 22 Mar 2026 05:48:44 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20260120-mtkdsi-v1-1-b0f4094f3ac3@gmail.com> In-Reply-To: <20260120-mtkdsi-v1-1-b0f4094f3ac3@gmail.com> From: Chun-Kuang Hu Date: Sun, 22 Mar 2026 12:48:32 +0000 X-Gmail-Original-Message-ID: X-Gm-Features: AaiRm51LgG71Rayap4Jr4WgpvsodcOgbZVoTNsW735vZ4_JuKqtb7WjSvvTg7sg Message-ID: Subject: Re: [PATCH] drm/mediatek: mtk_dsi: enable hs clock during pre-enable To: Gary Bisson Cc: Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Matthias Brugger , AngeloGioacchino Del Regno , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi, Gary: Gary Bisson =E6=96=BC 2026=E5=B9=B41=E6=9C=8820=E6= =97=A5=E9=80=B1=E4=BA=8C =E4=B8=8A=E5=8D=8811:37=E5=AF=AB=E9=81=93=EF=BC=9A > > Some bridges, such as the TI SN65DSI83, require the HS clock to be > running in order to lock its PLL during its own pre-enable function. > > Without this change, the bridge gives the following error: > sn65dsi83 14-002c: failed to lock PLL, ret=3D-110 > sn65dsi83 14-002c: Unexpected link status 0x01 > sn65dsi83 14-002c: reset the pipe > > Move the necessary functions from enable to pre-enable. Applied to mediatek-drm-next [1], thanks. [1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/= log/?h=3Dmediatek-drm-next Regards, Chun-Kuang. > > Signed-off-by: Gary Bisson > --- > Tested on Tungsten510 module with sn65dsi83 + tm070jdhg30 panel. > > Left mtk_dsi_set_mode() as part of the enable function to mimic what is > done in the Samsung DSIM driver which is known to be working the TI > bridge. > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 35 +++++++++++++++++---------------= --- > 1 file changed, 17 insertions(+), 18 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediate= k/mtk_dsi.c > index 0e2bcd5f67b7..b560245d1be9 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c > @@ -672,6 +672,21 @@ static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi= *dsi, u8 irq_flag, u32 t) > } > } > > +static void mtk_dsi_lane_ready(struct mtk_dsi *dsi) > +{ > + if (!dsi->lanes_ready) { > + dsi->lanes_ready =3D true; > + mtk_dsi_rxtx_control(dsi); > + usleep_range(30, 100); > + mtk_dsi_reset_dphy(dsi); > + mtk_dsi_clk_ulp_mode_leave(dsi); > + mtk_dsi_lane0_ulp_mode_leave(dsi); > + mtk_dsi_clk_hs_mode(dsi, 0); > + usleep_range(1000, 3000); > + /* The reaction time after pulling up the mipi signal for= dsi_rx */ > + } > +} > + > static int mtk_dsi_poweron(struct mtk_dsi *dsi) > { > struct device *dev =3D dsi->host.dev; > @@ -724,6 +739,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) > mtk_dsi_set_vm_cmd(dsi); > mtk_dsi_config_vdo_timing(dsi); > mtk_dsi_set_interrupt_enable(dsi); > + mtk_dsi_lane_ready(dsi); > + mtk_dsi_clk_hs_mode(dsi, 1); > > return 0; > err_disable_engine_clk: > @@ -769,30 +786,12 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi) > dsi->lanes_ready =3D false; > } > > -static void mtk_dsi_lane_ready(struct mtk_dsi *dsi) > -{ > - if (!dsi->lanes_ready) { > - dsi->lanes_ready =3D true; > - mtk_dsi_rxtx_control(dsi); > - usleep_range(30, 100); > - mtk_dsi_reset_dphy(dsi); > - mtk_dsi_clk_ulp_mode_leave(dsi); > - mtk_dsi_lane0_ulp_mode_leave(dsi); > - mtk_dsi_clk_hs_mode(dsi, 0); > - usleep_range(1000, 3000); > - /* The reaction time after pulling up the mipi signal for= dsi_rx */ > - } > -} > - > static void mtk_output_dsi_enable(struct mtk_dsi *dsi) > { > if (dsi->enabled) > return; > > - mtk_dsi_lane_ready(dsi); > mtk_dsi_set_mode(dsi); > - mtk_dsi_clk_hs_mode(dsi, 1); > - > mtk_dsi_start(dsi); > > dsi->enabled =3D true; > > --- > base-commit: 8f0b4cce4481fb22653697cced8d0d04027cb1e8 > change-id: 20260120-mtkdsi-29e4c84e7b38 > > Best regards, > -- > Gary Bisson >