From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-il1-f175.google.com (mail-il1-f175.google.com [209.85.166.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 45E8E13AA20 for ; Fri, 17 Jan 2025 15:53:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.166.175 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737129203; cv=none; b=N/U6/tFfZ2hD8WZ2QRchg1+sCFwszTEb8WvwiEKBbmz4UjwMe1LS91IFt7V6mLgAO6zoIoT8/ODvQ9D6FI9pr2++OOUqGDCzHa6CTO/+KxIOMEbLvA5JHQp8lKpZSZsAY3flkr3XV4PEYK6XczIyjikAuHYbA/yyAyGxEMQImaI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737129203; c=relaxed/simple; bh=46+7DC0p+j8Oo+OTPjLnRycJoqEvbhzAXxYaKMfRB4Q=; h=MIME-Version:References:In-Reply-To:From:Date:Message-ID:Subject: To:Cc:Content-Type; b=GjApagiuYvsrfATc1rNf9kvvViwBJGMGCKv9gWCZU4AQovPDYxkiofw9yUR30paSFThEW9j4kc/8Ub+1CiEeIdiqAQDkhl63PnSf2E/Cmb45I4kvvrmeG40SuU+b74bL0Gsqx7zNE9sFWexiFfsYRoNjUJefL+v9kmRpaZJ6DOs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=brainfault.org; spf=none smtp.mailfrom=brainfault.org; dkim=pass (2048-bit key) header.d=brainfault-org.20230601.gappssmtp.com header.i=@brainfault-org.20230601.gappssmtp.com header.b=Gn9qM1Hk; arc=none smtp.client-ip=209.85.166.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=brainfault.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=brainfault-org.20230601.gappssmtp.com header.i=@brainfault-org.20230601.gappssmtp.com header.b="Gn9qM1Hk" Received: by mail-il1-f175.google.com with SMTP id e9e14a558f8ab-3ce7a33ea70so7975505ab.3 for ; Fri, 17 Jan 2025 07:53:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20230601.gappssmtp.com; s=20230601; t=1737129200; x=1737734000; darn=vger.kernel.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=7E63vfoifeN0266UFl3CmBetwowaMxD5JK1imwgdXUU=; b=Gn9qM1HkQvKMPdS76IC2841C3RLajgTqvhoGFax+UX52LAqFs1YyUdS9oKQAHr8bKR wpVwZPpmmZ6SswtuLbbSBPKSbGR3H93uYmoPirCaibE4cktkNry49q5r0MpAn/9zh+19 hQodnuXMuybeUhA3qNOwCm3Q2i0ds6cb9TlWaZ6GNe+/OsOQChLIZn5CwqfxzHMlOi9O YmzF4ncprK943As6oQUcuq/guaAjeXBO9ebau0gnd4Mr3B0Vf4OgXUAq8rccM/7Zzthk xqJgZxIGLzzUHGmdrdSgqqOGkxOaTAnAaX7BDQa7ZZ5NKm90WEGaI9j9B8OzEkAUZO+L 32Sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737129200; x=1737734000; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7E63vfoifeN0266UFl3CmBetwowaMxD5JK1imwgdXUU=; b=abu2XP6fsg9GfhRh3bRyMEwvT51GtxCFFIF7O2qOoABFyC3sgDeaxvAOBWcKx/veGH mj8/FezMo7rciP/G+J9aITq9EwcqezM89phvLxdZW58Dx542t/rXiyBEqZ6ueufsdF6y CEx88MM2HUrAgIlKNQuOV4VHUYfoqYU3l195vsIFxNkCL63MAi5KjlbawUA/2iJg7qMk wVJW1slUXZisQ630wnT2lRPKYYrVqtJveY/SJYMVS3UqhRdBzQMar0uPXEZMg1/LP1pj DHznxURLDXnELakhBR5DqoRazv49W7c03YMm3exgWPCWAxOlNS4aL8mCuMnMWd7ybIGo GSzw== X-Forwarded-Encrypted: i=1; AJvYcCV8y/nusI0vTGdFBl+dvEALEvGOwgitlG8hE93usRWnujVviEfS7rRvabK9ULmdul4TQaILi1dsd9/h6Ig=@vger.kernel.org X-Gm-Message-State: AOJu0YzC8e4MOfdWhhJI+QpldN2fcMmTnSv34e4ncV2yByQ3kqBLvcVG NXHWfl6izqE3tmXXNkx3cWlckT93xM5VlUrkbvEsXxoMilO10AoFpShWetby4/cRfvz4RKlxv/u Sg0zpI5tOVILDd46avoCKrfaoZuAKDBH92ixJfYNSZxapUdKzHQI= X-Gm-Gg: ASbGnctSK80ThOrLN0Hs//e+36OLnKVoh1VV93hvlZ+xfaRUdoO72WPcPicRrx1Iek6 DBo2o/iWz/70F/Yh6rjDRXcBzJJcXlwnioqA0hb8= X-Google-Smtp-Source: AGHT+IEBFN0smf2/xMRte+rDa7NGbWs/o9tvwRI5JcpREJT1MjNqqoS6tgTwYNGAuHJRpxn2V9yfVn+I7RHCKX143xQ= X-Received: by 2002:a05:6e02:3783:b0:3ce:473d:9cba with SMTP id e9e14a558f8ab-3cf743c76e3mr22233015ab.5.1737129200267; Fri, 17 Jan 2025 07:53:20 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250116120710.51673-1-luxu.kernel@bytedance.com> <87ldv9afso.ffs@tglx> In-Reply-To: <87ldv9afso.ffs@tglx> From: Anup Patel Date: Fri, 17 Jan 2025 21:23:06 +0530 X-Gm-Features: AbW1kvZzN4IfK5cgNNHnHg3RTHxscMkyVKMwxU0HE34KLwsuPghy0qSAUSDRLIc Message-ID: Subject: Re: [PATCH] irqchip: riscv: Order normal writes and IPI writes To: Thomas Gleixner Cc: Charlie Jenkins , Xu Lu , paul.walmsley@sifive.com, palmer@dabbelt.com, lihangjing@bytedance.com, xieyongji@bytedance.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Thomas, On Fri, Jan 17, 2025 at 4:05=E2=80=AFPM Thomas Gleixner wrote: > > Charlie! > > On Thu, Jan 16 2025 at 13:09, Charlie Jenkins wrote: > > On Thu, Jan 16, 2025 at 08:07:10PM +0800, Xu Lu wrote: > >> Replace writel_relaxed() with writel() when issuing IPI to ensure all > >> previous write operations made by current CPU are visible to other CPU= s. > > > > Did you experience an ordering issue from this? > > That's not the right question. > > CPU 0 CPU 1 > store A // data > store B // IPI > IPI handler > load A > > The real question is whether the RISC-V memory model guarantees under > all circumstances that A is globally visible before the IPI handler > load. If so, then the writel_relaxed() is fine. If not, the fence is > required. > > That's not a question of observation. It's a question of facts defined > by the architecture. People have wasted months to analyze such fails > which tend to happen once every blue moon with no other trace than > "something went wrong" .... The RISC-V FENCE instruction distinguishes between normal memory operations and I/O operations in its predecessor and successor sets where r =3D normal read, w =3D normal write, i =3D I/O read, and o =3D I/O write. The ipi_mux_send_mask() does smp_mb__after_atomic() (equals to "fence rw,rw") before calling imsic_ipi_send(). This prevents ordering of normal memory writes in imsic_ipi_send() before smp_mb__after_atomic() in ipi_mux_send_mask() but it does not prevent I/O memory writes in imsic_ipi_send() to be ordered before smp_mb__after_atomic(). This means currently nothing prevents the I/O memory write in imsic_ipi_send() to be ordered before normal memory writes in ipi_mux_send_mask() hence there is a very unlikely possibility of an IPI handler on the target CPU seeing incorrect data. The conversion of writel_relaxed() to writel() in imsic_ipi_send() adds a "fence w,o" before the actual I/O memory write which ensures that I/O memory write is not ordered before normal memory writes. Based on the above, the conversion of writel_relaxed() to writel() in imsic_ipi_send() looks good to me. Regards, Anup