From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA9933B27E9 for ; Tue, 14 Apr 2026 13:02:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776171736; cv=none; b=WfUQhkYXLvh/xo8XwVbO/xRKT9ZXMFajux96up16VpIrD0JCcBta9/511ogtr7yk3Jo4o2OqhVhID1hvVqjBj42FUPRWFJMAh0LiLJPzgZCbPpcM68ZZbN4dWT0hJw9ddqw+F+Ln63tAKQWzjXxJN5Cpuxnjtj6lK0QxjbBhUFA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776171736; c=relaxed/simple; bh=u4TJHo+YjHnslthEruJo9GDBxeCUvBTQYDfL4pQBbjY=; h=MIME-Version:References:In-Reply-To:From:Date:Message-ID:Subject: To:Cc:Content-Type; b=QuhwZiM/3G4fIrWC57mhVbsIqlB7jDEH69dHMVJMhlaNis1Cbfj/CJeZNSfz8FpsNJGSk7mlCJz0pDH8fiQZvKEyacXGHg/N0AbI7JD9fvhGntAgazhCnpXzsPMZnMuVhzIcQ48e7nLykqPeOwzsinvImQml20ftwCqDqBoVmiU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=AnH//2Kb; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AnH//2Kb" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 79AF1C2BCB7 for ; Tue, 14 Apr 2026 13:02:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1776171736; bh=u4TJHo+YjHnslthEruJo9GDBxeCUvBTQYDfL4pQBbjY=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=AnH//2KbF3PvpjSxSPs5eXAlpniBjIX1/0z2XqTsFqjdc/7IgISBasicDrXq6hpB6 hkZpIzZ7+QKRWs+VbmW0F3q5nFhQVTPqoBEgmH7urPK31aKREKnWfTtjWRUB4eGJ2G 6CFfb/q0amesQcfzNEwawHDvYx4Li48N1KVKnpiHeIbYV0nm8Loce+1iX22BoQ0G1V c7wJzfWeE47VCR/f19oLIYqPTtXpm1HxoKyvhm6VEA1D9j571hU0gWTzek0/kvn75T /Qk7ZqcZbYhgiZCWLAPK8g+zYcXkRBDEnERE62+XB5FjNcXOHZFEP+91y6jw25kzI+ hsQnZxvAazRWw== Received: by mail-ej1-f52.google.com with SMTP id a640c23a62f3a-b9e00649769so220392866b.3 for ; Tue, 14 Apr 2026 06:02:16 -0700 (PDT) X-Forwarded-Encrypted: i=1; AFNElJ8a18pvvzmPyWjXGls+11qTgqCh3f+H2evu0x5Y+We5P7I4CLB7XXVcesXuCel8UDIxQcDmbQLqzkr9Tls=@vger.kernel.org X-Gm-Message-State: AOJu0YwPmHdKDdq7ovja0a/dXy1MHo1wbD3Z47jxKx6zcsQB7U8ES5QS /3S9ec85J04Mevc+i7vv5KWI0c8vIl1hlhLYNhMbBx+z6WdCpcElHJc4c0Jd98gTSvt9CyEqYuu LAW2aRyxFq3ybM6iXliM+Yae8uQc1nH8= X-Received: by 2002:a17:907:e981:b0:b97:1d24:bfed with SMTP id a640c23a62f3a-b9d72991f8dmr1023073166b.41.1776171734952; Tue, 14 Apr 2026 06:02:14 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20260330094845.39-1-lisa@bytefly.space> In-Reply-To: From: Huacai Chen Date: Tue, 14 Apr 2026 21:02:22 +0800 X-Gmail-Original-Message-ID: X-Gm-Features: AQROBzDr5Y6mV-w1AlzgpRhNJFL84mEEY5BS6HeG8SIhgAT17GHgHp1Ia3Fv5cM Message-ID: Subject: Re: [PATCH] LoongArch: Align FPU register state to 32 bytes To: Lisa Robinson Cc: WANG Xuerui , loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, Apr 14, 2026 at 4:20=E2=80=AFPM Huacai Chen = wrote: > > On Sat, Apr 11, 2026 at 9:10=E2=80=AFPM Huacai Chen wrote: > > > > Applied, thanks. > I'm sorry, I reverted this patch because it breaks the partial copy > optimization in arch_dup_task_struct(). Fixed as this: https://github.com/chenhuacai/linux/commit/c1365bc97d609438809d5d44d338adfc= 09767d6f Huacai > > Huacai > > > > > Huacai > > > > On Mon, Mar 30, 2026 at 5:49=E2=80=AFPM Lisa Robinson wrote: > > > > > > Move fpr to the beginning of struct loongarch_fpu so it is naturally > > > aligned to FPU_ALIGN (32 bytes), improving 256-bit SIMD (LASX) contex= t > > > switch performance. > > > > > > Signed-off-by: Lisa Robinson > > > --- > > > arch/loongarch/include/asm/processor.h | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/arch/loongarch/include/asm/processor.h b/arch/loongarch/= include/asm/processor.h > > > index c3bc44b5f5b3..ce8b953f8c79 100644 > > > --- a/arch/loongarch/include/asm/processor.h > > > +++ b/arch/loongarch/include/asm/processor.h > > > @@ -80,10 +80,10 @@ BUILD_FPR_ACCESS(32) > > > BUILD_FPR_ACCESS(64) > > > > > > struct loongarch_fpu { > > > + union fpureg fpr[NUM_FPU_REGS]; > > > uint64_t fcc; /* 8x8 */ > > > uint32_t fcsr; > > > uint32_t ftop; > > > - union fpureg fpr[NUM_FPU_REGS]; > > > }; > > > > > > struct loongarch_lbt { > > > -- > > > 2.53.0 > > >