From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S938799AbcKQG0k (ORCPT ); Thu, 17 Nov 2016 01:26:40 -0500 Received: from mail-wm0-f51.google.com ([74.125.82.51]:36693 "EHLO mail-wm0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751059AbcKQG0j (ORCPT ); Thu, 17 Nov 2016 01:26:39 -0500 MIME-Version: 1.0 In-Reply-To: <1476628518-20450-1-git-send-email-boris.brezillon@free-electrons.com> References: <1476628518-20450-1-git-send-email-boris.brezillon@free-electrons.com> From: Peter Pan Date: Thu, 17 Nov 2016 14:26:37 +0800 Message-ID: Subject: Re: [PATCH v2 0/7] mtd: nand: Abstract away the NAND interface type To: Boris Brezillon Cc: Richard Weinberger , linux-mtd@lists.infradead.org, David Woodhouse , Brian Norris , Ezequiel Garcia , linux-kernel@vger.kernel.org, "peterpandong@micron.com" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Boris, On Sun, Oct 16, 2016 at 10:35 PM, Boris Brezillon wrote: > Hi, > > This series is aiming at providing a generic NAND layer to share code > between different NAND based devices. > > We currently have 3 different interfaces to interact with NANDs: > - Raw NANDs > - OneNANDs > - SPI NANDs > > Apart from the way these NAND devices are accessed they have a lot > in common, like the way the memory is organized, or their constraints. > This is usually a good sign that some work should be done to factorize > the code. > > This work has been started by Peter who wanted to re-use the BBT > code for its SPI-NAND driver. But I think we can push it further > other stuff (the software ECC implementation, or the way offsets are > converted to block/page number). > > Peter, can you please review/test this version, and if possible, post > the code you've done to support SPI NANDs. > I already finished review and test work. The BBT works well after I applied my modification which I already sent to your by email. I tried to build a new BBT on a new NAND and then mark one block to bad. Both works well. My test platform is Xilinx Zed board. I will try to rebase my SPI NAND patch on your patch and send it out. It will take me some time because I'm quite busy with other company affairs. Thanks, Peter Pan