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Mon, 12 Feb 2024 09:02:07 -0800 (PST) X-Google-Smtp-Source: AGHT+IFCFax7iOyuTjts+iORw8GZdLYnDFGPnLUiSaDSP/ju4W8BO+P1UaZiXkLE5e/PfH3uG4VPrFduuFeVfmg1qE8= X-Received: by 2002:a05:6808:138b:b0:3c0:31e5:35f1 with SMTP id c11-20020a056808138b00b003c031e535f1mr6116210oiw.36.1707757327107; Mon, 12 Feb 2024 09:02:07 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <91c797997b57056224571e22362321a23947172f.1705965635.git.isaku.yamahata@intel.com> In-Reply-To: <91c797997b57056224571e22362321a23947172f.1705965635.git.isaku.yamahata@intel.com> From: Paolo Bonzini Date: Mon, 12 Feb 2024 18:01:54 +0100 Message-ID: Subject: Re: [PATCH v18 040/121] KVM: x86/mmu: Disallow fast page fault on private GPA To: isaku.yamahata@intel.com Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, isaku.yamahata@gmail.com, erdemaktas@google.com, Sean Christopherson , Sagi Shahar , Kai Huang , chen.bo@intel.com, hang.yuan@intel.com, tina.zhang@intel.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, Jan 23, 2024 at 12:55=E2=80=AFAM wrote: > > From: Isaku Yamahata > > TDX requires TDX SEAMCALL to operate Secure EPT instead of direct memory > access and TDX SEAMCALL is heavy operation. Fast page fault on private G= PA > doesn't make sense. Disallow fast page fault on private GPA. > > Signed-off-by: Isaku Yamahata > Reviewed-by: Paolo Bonzini > --- > arch/x86/kvm/mmu/mmu.c | 12 ++++++++++-- > 1 file changed, 10 insertions(+), 2 deletions(-) > > diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c > index b2924bd9b668..54d4c8f1ba68 100644 > --- a/arch/x86/kvm/mmu/mmu.c > +++ b/arch/x86/kvm/mmu/mmu.c > @@ -3339,8 +3339,16 @@ static int kvm_handle_noslot_fault(struct kvm_vcpu= *vcpu, > return RET_PF_CONTINUE; > } > > -static bool page_fault_can_be_fast(struct kvm_page_fault *fault) > +static bool page_fault_can_be_fast(struct kvm *kvm, struct kvm_page_faul= t *fault) > { > + /* > + * TDX private mapping doesn't support fast page fault because th= e EPT > + * entry is read/written with TDX SEAMCALLs instead of direct mem= ory > + * access. > + */ > + if (kvm_is_private_gpa(kvm, fault->addr)) > + return false; I think this does not apply to SNP? If so, it would be better to check the SPTE against the shared-page mask inside the do...while loop. Paolo > /* > * Page faults with reserved bits set, i.e. faults on MMIO SPTEs,= only > * reach the common page fault handler if the SPTE has an invalid= MMIO > @@ -3450,7 +3458,7 @@ static int fast_page_fault(struct kvm_vcpu *vcpu, s= truct kvm_page_fault *fault) > u64 *sptep; > uint retry_count =3D 0; > > - if (!page_fault_can_be_fast(fault)) > + if (!page_fault_can_be_fast(vcpu->kvm, fault)) > return ret; > > walk_shadow_page_lockless_begin(vcpu); > -- > 2.25.1 >