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charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, May 8, 2025 at 2:13=E2=80=AFPM Konrad Dybcio wrote: > > From: Konrad Dybcio > > Instead of setting it on a gpu-per-gpu basis, converge it to the > intended "is A650 family or A7xx". Can we also set this based on the UBWC version? Connor > > Signed-off-by: Konrad Dybcio > --- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++--------- > 1 file changed, 3 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/= adreno/a6xx_gpu.c > index 5fe0e8e72930320282a856e1ff77994865360854..e1eab0906b6c460528da82a94= a285ef181e0b479 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -593,7 +593,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *g= pu) > return -EINVAL; > > gpu->ubwc_config.rgb565_predicator =3D 0; > - gpu->ubwc_config.uavflagprd_inv =3D 0; > gpu->ubwc_config.min_acc_len =3D 0; > gpu->ubwc_config.ubwc_swizzle =3D 0x6; > gpu->ubwc_config.macrotile_mode =3D 0; > @@ -615,15 +614,12 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu = *gpu) > if (adreno_is_a619_holi(gpu)) > gpu->ubwc_config.highest_bank_bit =3D 0; > > - if (adreno_is_a621(gpu)) { > + if (adreno_is_a621(gpu)) > gpu->ubwc_config.highest_bank_bit =3D 0; > - gpu->ubwc_config.uavflagprd_inv =3D 2; > - } > > if (adreno_is_a623(gpu)) { > gpu->ubwc_config.highest_bank_bit =3D 3; > gpu->ubwc_config.rgb565_predicator =3D 1; > - gpu->ubwc_config.uavflagprd_inv =3D 2; > gpu->ubwc_config.macrotile_mode =3D 1; > } > > @@ -638,21 +634,18 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu = *gpu) > /* TODO: get ddr type from bootloader and use 2 for LPDDR= 4 */ > gpu->ubwc_config.highest_bank_bit =3D 3; > gpu->ubwc_config.rgb565_predicator =3D 1; > - gpu->ubwc_config.uavflagprd_inv =3D 2; > gpu->ubwc_config.macrotile_mode =3D 1; > } > > if (adreno_is_a663(gpu)) { > gpu->ubwc_config.highest_bank_bit =3D 0; > gpu->ubwc_config.rgb565_predicator =3D 1; > - gpu->ubwc_config.uavflagprd_inv =3D 2; > gpu->ubwc_config.macrotile_mode =3D 1; > gpu->ubwc_config.ubwc_swizzle =3D 0x4; > } > > if (adreno_is_7c3(gpu)) { > gpu->ubwc_config.highest_bank_bit =3D 1; > - gpu->ubwc_config.uavflagprd_inv =3D 2; > gpu->ubwc_config.macrotile_mode =3D 1; > } > > @@ -667,6 +660,7 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *g= pu) > static void a6xx_set_ubwc_config(struct msm_gpu *gpu) > { > struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); > + u8 uavflagprd_inv =3D adreno_is_a650_family(adreno_gpu) || adreno= _is_a7xx(adreno_gpu) ? 2 : 0; > const struct qcom_ubwc_cfg_data *cfg =3D adreno_gpu->common_ubwc_= cfg; > u32 hbb =3D adreno_gpu->ubwc_config.highest_bank_bit; > bool amsbc =3D cfg->ubwc_enc_version >=3D UBWC_3_0; > @@ -689,7 +683,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) > > gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, > level2_swizzling_dis << 12 | hbb_hi << 10 | > - adreno_gpu->ubwc_config.uavflagprd_inv << 4 | > + uavflagprd_inv << 4 | > adreno_gpu->ubwc_config.min_acc_len << 3 | > hbb_lo << 1 | ubwc_mode); > > > -- > 2.49.0 >