From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4762C41A509 for ; Mon, 17 Aug 2026 12:35:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786970114; cv=none; b=YDkvRaKIrjufetuQwPknH4ZuAqhzkVwfqW6iwyfimVr890H3tqRybIyILHPtoF/qn4Ixbq5jCcFBThR8eDc7cVs1XwnFo000aeaiY1D11BI0n4dPWzFoK3XOf08oJrFFytnpOEqir2U6tvllrThoeX9Uu3O7ikzaUqYQ0C4Hd8s= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786970114; c=relaxed/simple; bh=1A6ly4O2qy9jX3fh5J0Jn7vpphCQE+kxQ2Yqd7sJMh4=; h=MIME-Version:References:In-Reply-To:From:Date:Message-ID:Subject: To:Cc:Content-Type; b=BuTtNKuTMpRNWDRkVJVNsy0viOJUuFGcw2Wg70W4KFpytdWwb8dkAMmKlVLjA1m2I6GkGl3qjiUdgOVmRO2MzT1dJBb60kiA7eiIlgwXCLswhB+E1+wOuD4SbeJ34E/FLVwC2BIKVP19R7tcyOvKuzv2+vC7hoW+cgOdXSA5FAI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=csseRKHQ; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="csseRKHQ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EBAEC1F00AC4 for ; Mon, 17 Aug 2026 12:35:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1786970113; bh=F0BoI1B2SW1Gn2SrMpAVpRAmC4OHC4tZa8DJdUfqO2A=; h=References:In-Reply-To:From:Date:Subject:To:Cc; b=csseRKHQX5NyNSjcQKvlDmFWeo5PfxggOGtuQpn/ZKn3CT0o/BTbkT/jpLdYDFc6g 6m+X6vBujvUDQ/iAfwKZ3btQYHMDBk12RR4oCjjdYhEbCUy+3GUxjIfsI9Bg/gyL+4 T4jLVMBE+OiddY33VJ3RFdjS777uavuRurNh1j299B5DSr3W4gxhrwFMvKKUySeebG H6TobWVt/hJgNN+zPs3GGzbHMN0Cec7n4IdOfMDJ4wmewDkHwhx0qX3YKwM/DYm7/X dMmMMN2CDqwGdl90e3IIkL3pYpPEUaHUsph2c72yd4FLhNjV82JToznER+tsEqGE2I qZTh4BSHHlaaA== Received: by mail-lf1-f42.google.com with SMTP id 2adb3069b0e04-5aec201b582so2957860e87.1 for ; Mon, 17 Aug 2026 05:35:12 -0700 (PDT) X-Forwarded-Encrypted: i=1; AHgh+RpBZ8LD/KnZIomlGGPZwSNWCNxWT6wmCs3+S6P0p29NuSaMhK8jx4FHfoaWklJk540q5yOrOydjZlWh6zg=@vger.kernel.org X-Gm-Message-State: AOJu0YyVZwC371LRTK8ZwuFWIs4ulbrWKUbJ1VnX4GI/VUekek0dPsOt m0zrfftdXIzYGrTo4QRmp6bGHhf5u8v+8VNH/VJ50NagBU8vhOGX8LQkeyO6UeaBnOBSh3L6FYk UTjKZ24tovz68FIpWmFEahtFM3P1Rb0E= X-Received: by 2002:a05:6512:66cf:b0:5b2:e956:b459 with SMTP id 2adb3069b0e04-5b45915e1e5mr2876859e87.12.1786970111723; Mon, 17 Aug 2026 05:35:11 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20260814-kuno-soc-support-v2-0-3079794f0f73@oss.qualcomm.com> In-Reply-To: <20260814-kuno-soc-support-v2-0-3079794f0f73@oss.qualcomm.com> From: Linus Walleij Date: Mon, 17 Aug 2026 14:34:58 +0200 X-Gmail-Original-Message-ID: X-Gm-Features: AcwNN1VfwHAQiclbXAp71Kv0t_X4ZrB4Vq7QuyBm6v6ehpWFekFj-AwEo8Rc4XI Message-ID: Subject: Re: [PATCH v2 00/15] Add initial support for Qualcomm Kuno SoC To: Hardeep Sharma Cc: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Michael Turquette , Stephen Boyd , Brian Masney , Taniya Das , Georgi Djakov , Bartosz Golaszewski , Thomas Gleixner , Radu Rendec , Robert Marko , Guru Das Srinagesh , linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Mukesh Savaliya , Dmitry Baryshkov , Bartosz Golaszewski Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, Aug 14, 2026 at 9:32=E2=80=AFAM Hardeep Sharma wrote: > This series adds initial support for the Qualcomm Kuno SoC and the Kuno > IDP reference board. > > Kuno is a 32-bit ARM (Cortex-A7) Qualcomm platform. This series brings up > the essential SoC infrastructure required to boot to a serial console: > > - Global Clock Controller (GCC) and RPMh clock controller > - RPMh power domains > - Interconnect (NoC) provider > - TLMM pin controller > - PDC interrupt controller and SCM firmware interface > - Devicetree for the SoC and the Kuno IDP board > > The soc: qcom: geni-se patch allows the GENI serial engine driver to be > selected on 32-bit ARM Qualcomm SoCs, which the debug UART console > depends on. > > Signed-off-by: Hardeep Sharma I understand if you wanna be a bit Greta Garbo mysterious about this SoC but patch 10 gives the hardware away: /* GCC clocks */ +#define GCC_EMAC0_AXI_CLK 7 Aha it has an ethernet interface. +#define GCC_PCIE_0_CLKREF_EN 22 Aha it has PCI. +#define GCC_SDCC4_AHB_CLK 53 Aha it has SD/MMC cards. +#define GCC_USB20_MASTER_CLK 58 Aha it has USB2. +#define GCC_USB3_PRIM_CLKREF_EN 65 And USB 3. Other files give away that it also has a modem. Etc. So what about writing a bit more about the platform in the commit message? For a surprising brand new ARM32 platform we (the SoC maintainers) are goin= g to be curious to know why this is happening in 2026. Yours, Linus Walleij