From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96D3C32D44F for ; Tue, 3 Feb 2026 23:44:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770162280; cv=none; b=CSMDmsXWoxrAfyV4l4BaE/Bo1lVt19oXErogsOsfOc68Spv/+weLfl2ibqIwiUOQfN56kVRNmg7Kr4nb4Gn25Ccr9e7r/EdcpcekrynYN7oRDBIb7iMs8l19hX2Y8XP8Et3szAlu09y7Sd8sK5jKzfUq+CvDcwrnB1amVTVwbn4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770162280; c=relaxed/simple; bh=MUtAEzuFZ3UXsgeYeGcULd0s9lsr291/wS31tUAYPQI=; h=MIME-Version:References:In-Reply-To:From:Date:Message-ID:Subject: To:Cc:Content-Type; b=PkQL90Z8x3jMzJvpM3L1iCk3+wUcY3A1jFWYSiXFoaUMJZ8aP7RMq6mebXTeeEX3vCETt6PWMRm620SeBGJMx5h1XvThlC8bhKvZaauTfvZRpUXPI5/Lyvf1cccBBBHTWoG6aAFFcS5WNR3ADDYzruRjFroMUASWhOOckzeZDOg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ugcyN0Rq; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ugcyN0Rq" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 56EA0C2BCB0 for ; Tue, 3 Feb 2026 23:44:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1770162280; bh=MUtAEzuFZ3UXsgeYeGcULd0s9lsr291/wS31tUAYPQI=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=ugcyN0RqC48lMQVC290mr54/cSG8mF5qG6qEw1bXtuEg1AHRMdgpEol4MTB4WYgbx 2xgqlBNWqkJckBepT2lyA7KPKwAVTR7exlJt6+nKU49bLYyk6a32A0JXHEgkYdX0JW JdKy89rOSuHUxQGG36O3GomJnrxi8DRpkj9qqaL1u59b5X03z9pAKndSF27sExk6Mu e+wEhvO8nkNb10Lh7E62jU/jKYzK+2n8Cn3jkoSu8teRtumFaYuuD7lBca1tjzvYHH DNwMUzf8L2cy3eu0zdga38VJVA/+z07Ak3oWCQxVORf+z7cadCUrLBIMwDdqHvpyx/ 3Nl558QdYMMaA== Received: by mail-yx1-f42.google.com with SMTP id 956f58d0204a3-649bd1f08acso276714d50.1 for ; Tue, 03 Feb 2026 15:44:40 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCVob5Az6vXEsktz2dWEzC3PMbWo5ftM6HAvtIYzUgjqNXJ8NJafrL2xsNOFhh0QVPCfqhEFJq+rhx+gn1A=@vger.kernel.org X-Gm-Message-State: AOJu0YxMw8KPlnI9QFt1VGiwqfBJoEgS3rFMSOIQuGQZdUvY/aAwvzZU RPGQGRTDz2ZUz3253B8yi2tmnY8x+/aj1SBAmB+k8sW96LmQYDFoW8KxUl/FcuwXstYUa2pVV0I R4n3Wa1/dKfktsp5JHuMg/GzP+ZyhrQg= X-Received: by 2002:a53:d8c6:0:b0:645:68cf:2bf4 with SMTP id 956f58d0204a3-649db4ac96bmr877835d50.77.1770162279637; Tue, 03 Feb 2026 15:44:39 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20260203-dev-b4-aaeon-mcu-driver-v3-0-0a19432076ac@bootlin.com> <20260203-dev-b4-aaeon-mcu-driver-v3-4-0a19432076ac@bootlin.com> In-Reply-To: <20260203-dev-b4-aaeon-mcu-driver-v3-4-0a19432076ac@bootlin.com> From: Linus Walleij Date: Wed, 4 Feb 2026 00:44:27 +0100 X-Gmail-Original-Message-ID: X-Gm-Features: AZwV_QjuysNBoHyalaty048gguXHT55tueRC1-zJSip9FADgZXaoN46HJGRIgaE Message-ID: Subject: Re: [PATCH v3 4/5] gpio: aaeon: Add GPIO driver for SRG-IMX8P MCU To: "Thomas Perrot (Schneider Electric)" Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , =?UTF-8?B?SsOpcsOpbWllIERhdXRoZXJpYmVz?= , Wim Van Sebroeck , Guenter Roeck , Lee Jones , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-watchdog@vger.kernel.org, Thomas Petazzoni Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, Feb 3, 2026 at 5:21=E2=80=AFPM Thomas Perrot (Schneider Electric) wrote: > Add GPIO driver for the Aaeon SRG-IMX8P embedded controller. This > driver supports 7 GPO (General Purpose Output) pins and 12 GPIO pins > that can be configured as inputs or outputs. > > The driver implements proper state management for GPO pins (which are > output-only) and full direction control for GPIO pins. During probe, > all pins are reset to a known state (GPOs low, GPIOs as inputs) to > prevent undefined behavior across system reboots, as the MCU does not > reset GPIO states on soft reboot. > > Co-developed-by: J=C3=A9r=C3=A9mie Dautheribes (Schneider Electric) > Signed-off-by: J=C3=A9r=C3=A9mie Dautheribes (Schneider Electric) > Signed-off-by: Thomas Perrot (Schneider Electric) Looks good to me! Reviewed-by: Linus Walleij Yours, Linus Walleij