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Mon, 26 Oct 2026 11:25:27 -0700 (PDT) X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 References: <20261025040046.1602-1-atharvatiwarilinuxdev@gmail.com> <20261025040046.1602-11-atharvatiwarilinuxdev@gmail.com> In-Reply-To: <20261025040046.1602-11-atharvatiwarilinuxdev@gmail.com> From: Alex Deucher Date: Mon, 26 Oct 2026 14:25:15 -0400 X-Gm-Features: AclHuK-iVje5ZZPGXAxueHXGbehXRgBbIH4abpn4VFZrQQC5igwZxtMQm-2wnbg Message-ID: Subject: Re: [PATCH 10/13] drm/amdgpu: Catch register access while GMUX keeps the GPU off To: Atharva Tiwari Cc: Andre Eikmeyer , Bjorn Helgaas , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "H. Peter Anvin" , Alex Deucher , =?UTF-8?Q?Christian_K=C3=B6nig?= , David Airlie , Simona Vetter , Harry Wentland , Leo Li , Rodrigo Siqueira , Kenneth Feng , Hans de Goede , =?UTF-8?Q?Ilpo_J=C3=A4rvinen?= , "open list:PCI SUBSYSTEM" , "open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "open list:RADEON and AMDGPU DRM DRIVERS" , "open list:DRM DRIVERS" , "open list:X86 PLATFORM DRIVERS" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Sun, Oct 25, 2026 at 12:26=E2=80=AFAM Atharva Tiwari wrote: > > From: Andre Eikmeyer > > As mentioned previous any access to the GPU when the GMUX has > shut off the rails results in a CPU CATTER, skip and report > any register access after the GPU was runtime suspended for GMUX power-of= f. > > Signed-off-by: Andre Eikmeyer > --- > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++ > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 ++++ > drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 ++++ > .../gpu/drm/amd/amdgpu/amdgpu_reg_access.c | 24 +++++++++++++++++++ > 4 files changed, 36 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/am= dgpu/amdgpu.h > index 6fd607587..ac8dfc3ab 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > @@ -881,6 +881,8 @@ struct amdgpu_device { > /* enable runtime pm on the device */ > bool in_runpm; > bool has_pr3; > + /* GMUX has cut power, any register access would hang the PEG lin= k */ > + bool gmux_off; You can drop this. Nothing about this is GMUX specific. > > bool ucode_sysfs_en; > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm= /amd/amdgpu/amdgpu_device.c > index c1f196242..8185934b4 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > @@ -946,6 +946,11 @@ bool amdgpu_device_skip_hw_access(struct amdgpu_devi= ce *adev) > if (adev->no_hw_access) > return true; > > + if (unlikely(READ_ONCE(adev->gmux_off))) { > + WARN_RATELIMIT(1, "%s: register access while powered off = by GMUX\n", > + dev_name(adev->dev)); > + return true; > + } > #ifdef CONFIG_LOCKDEP > /* > * This is a bit complicated to understand, so worth a comment. W= hat we assert > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/am= d/amdgpu/amdgpu_drv.c > index 5ad7b6dd8..135798c76 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > @@ -2932,6 +2932,9 @@ static int amdgpu_pmops_runtime_suspend(struct devi= ce *dev) > amdgpu_device_baco_enter(adev); > } > > + if (adev->pm.rpm_mode =3D=3D AMDGPU_RUNPM_GMUX) > + WRITE_ONCE(adev->gmux_off, true); > + > dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); > > return 0; > @@ -2960,6 +2963,8 @@ static int amdgpu_pmops_runtime_resume(struct devic= e *dev) > if (adev->pm.rpm_mode =3D=3D AMDGPU_RUNPM_NONE) > return -EINVAL; > > + WRITE_ONCE(adev->gmux_off, false); > + > /* Avoids registers access if device is physically gone */ > if (!pci_device_is_present(adev->pdev)) > adev->no_hw_access =3D true; > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c b/drivers/gpu= /drm/amd/amdgpu/amdgpu_reg_access.c > index 7468855c1..bb5dbeb7f 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c > @@ -594,6 +594,9 @@ u32 amdgpu_device_indirect_rreg(struct amdgpu_device = *adev, u32 reg_addr) > void __iomem *pcie_data_offset; > u32 r; > > + if (amdgpu_device_skip_hw_access(adev)) > + return 0; > + > pcie_index =3D adev->nbio.funcs->get_pcie_index_offset(adev); > pcie_data =3D adev->nbio.funcs->get_pcie_data_offset(adev); > > @@ -677,6 +680,12 @@ u64 amdgpu_device_indirect_rreg64(struct amdgpu_devi= ce *adev, u32 reg_addr) > void __iomem *pcie_data_offset; > u64 r; > > + if (amdgpu_device_skip_hw_access(adev)) > + return 0; > + > + if (amdgpu_device_skip_hw_access(adev)) > + return 0; Duplicate check here. Alex > + > pcie_index =3D adev->nbio.funcs->get_pcie_index_offset(adev); > pcie_data =3D adev->nbio.funcs->get_pcie_data_offset(adev); > > @@ -706,6 +715,9 @@ u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_d= evice *adev, u64 reg_addr) > void __iomem *pcie_data_offset; > u64 r; > > + if (amdgpu_device_skip_hw_access(adev)) > + return 0; > + > pcie_index =3D adev->nbio.funcs->get_pcie_index_offset(adev); > pcie_data =3D adev->nbio.funcs->get_pcie_data_offset(adev); > if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offs= et)) > @@ -762,6 +774,9 @@ void amdgpu_device_indirect_wreg(struct amdgpu_device= *adev, u32 reg_addr, > void __iomem *pcie_index_offset; > void __iomem *pcie_data_offset; > > + if (amdgpu_device_skip_hw_access(adev)) > + return; > + > pcie_index =3D adev->nbio.funcs->get_pcie_index_offset(adev); > pcie_data =3D adev->nbio.funcs->get_pcie_data_offset(adev); > > @@ -784,6 +799,9 @@ void amdgpu_device_indirect_wreg_ext(struct amdgpu_de= vice *adev, u64 reg_addr, > void __iomem *pcie_index_hi_offset; > void __iomem *pcie_data_offset; > > + if (amdgpu_device_skip_hw_access(adev)) > + return; > + > pcie_index =3D adev->nbio.funcs->get_pcie_index_offset(adev); > pcie_data =3D adev->nbio.funcs->get_pcie_data_offset(adev); > if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offs= et)) > @@ -832,6 +850,9 @@ void amdgpu_device_indirect_wreg64(struct amdgpu_devi= ce *adev, u32 reg_addr, > void __iomem *pcie_index_offset; > void __iomem *pcie_data_offset; > > + if (amdgpu_device_skip_hw_access(adev)) > + return; > + > pcie_index =3D adev->nbio.funcs->get_pcie_index_offset(adev); > pcie_data =3D adev->nbio.funcs->get_pcie_data_offset(adev); > > @@ -861,6 +882,9 @@ void amdgpu_device_indirect_wreg64_ext(struct amdgpu_= device *adev, u64 reg_addr, > void __iomem *pcie_index_hi_offset; > void __iomem *pcie_data_offset; > > + if (amdgpu_device_skip_hw_access(adev)) > + return; > + > pcie_index =3D adev->nbio.funcs->get_pcie_index_offset(adev); > pcie_data =3D adev->nbio.funcs->get_pcie_data_offset(adev); > if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offs= et)) > -- > 2.55.0 >