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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Christian, On Sat, Sep 27, 2025 at 3:02=E2=80=AFPM Christian Hewitt wrote: [...] > @@ -894,6 +908,10 @@ static void meson_vclk_set(struct meson_drm *priv, > m =3D 0xf7; > frac =3D vic_alternate_clock ? 0x8148 : 0x10000; > break; > + case 4830000: > + m =3D 0xc9; > + frac =3D 0xd560; > + break; Initially I thought this was wrong because it's only added for the G12A (which is also used on G12B and SM1) code-path, leaving out the GX SoCs. Was the 2560x1440 mode tested on a computer monitor or a TV? I suspect it's the former, so I think it expected the code to take the MESON_VCLK_TARGET_DMT path, which automatically calculates m and frac. I'll give it a try on Friday as I do have a computer monitor with that resolution - so any hints for testing are welcome! Best regards, Martin