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Wed, 25 Feb 2026 00:20:30 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20260120-mtkdsi-v1-1-b0f4094f3ac3@gmail.com> <80cecc13015aca7fe68dd40845e60af4bad42223.camel@mediatek.com> In-Reply-To: <80cecc13015aca7fe68dd40845e60af4bad42223.camel@mediatek.com> From: Chen-Yu Tsai Date: Wed, 25 Feb 2026 16:20:19 +0800 X-Gm-Features: AaiRm53aktJkvWRSs_OtrFpEUnAjkj1Xocp5KjXoLsN4g3Olmuw0jfNPNr4TOdc Message-ID: Subject: Re: [PATCH] drm/mediatek: mtk_dsi: enable hs clock during pre-enable To: =?UTF-8?B?Q0sgSHUgKOiDoeS/iuWFiSk=?= Cc: "p.zabel@pengutronix.de" , "chunkuang.hu@kernel.org" , AngeloGioacchino Del Regno , "airlied@gmail.com" , "bisson.gary@gmail.com" , "simona@ffwll.ch" , "matthias.bgg@gmail.com" , "dri-devel@lists.freedesktop.org" , "linux-mediatek@lists.infradead.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, Feb 25, 2026 at 2:20=E2=80=AFPM CK Hu (=E8=83=A1=E4=BF=8A=E5=85=89)= wrote: > > On Tue, 2026-01-20 at 12:36 +0100, Gary Bisson wrote: > > External email : Please do not click links or open attachments until yo= u have verified the sender or the content. > > > > > > Some bridges, such as the TI SN65DSI83, require the HS clock to be > > running in order to lock its PLL during its own pre-enable function. > > > > Without this change, the bridge gives the following error: > > sn65dsi83 14-002c: failed to lock PLL, ret=3D-110 > > sn65dsi83 14-002c: Unexpected link status 0x01 > > sn65dsi83 14-002c: reset the pipe > > > > Move the necessary functions from enable to pre-enable. > > Looks good to me, but this change the flow for all SoC and panel, > so I would wait for more SoC and more panel test. > > Reviewed-by: CK Hu Tested-by: Chen-Yu Tsai # Chromebooks Tested on: - MT8173 Hana (Telesu) w/ PS8640 bridge - MT8183 Krane w/ DSI panel - MT8183 Juniper w/ ANX7625 bridge - MT8186 Tentacruel w/ PS8640 bridge - MT8186 Steelix w/ PS8640 bridge No regressions observed. > > Signed-off-by: Gary Bisson > > --- > > Tested on Tungsten510 module with sn65dsi83 + tm070jdhg30 panel. > > > > Left mtk_dsi_set_mode() as part of the enable function to mimic what is > > done in the Samsung DSIM driver which is known to be working the TI > > bridge. > > --- > > drivers/gpu/drm/mediatek/mtk_dsi.c | 35 +++++++++++++++++-------------= ----- > > 1 file changed, 17 insertions(+), 18 deletions(-) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/media= tek/mtk_dsi.c > > index 0e2bcd5f67b7..b560245d1be9 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c > > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c > > @@ -672,6 +672,21 @@ static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_d= si *dsi, u8 irq_flag, u32 t) > > } > > } > > > > +static void mtk_dsi_lane_ready(struct mtk_dsi *dsi) > > +{ > > + if (!dsi->lanes_ready) { > > + dsi->lanes_ready =3D true; > > + mtk_dsi_rxtx_control(dsi); > > + usleep_range(30, 100); > > + mtk_dsi_reset_dphy(dsi); > > + mtk_dsi_clk_ulp_mode_leave(dsi); > > + mtk_dsi_lane0_ulp_mode_leave(dsi); > > + mtk_dsi_clk_hs_mode(dsi, 0); > > + usleep_range(1000, 3000); > > + /* The reaction time after pulling up the mipi signal f= or dsi_rx */ > > + } > > +} > > + > > static int mtk_dsi_poweron(struct mtk_dsi *dsi) > > { > > struct device *dev =3D dsi->host.dev; > > @@ -724,6 +739,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) > > mtk_dsi_set_vm_cmd(dsi); > > mtk_dsi_config_vdo_timing(dsi); > > mtk_dsi_set_interrupt_enable(dsi); > > + mtk_dsi_lane_ready(dsi); > > + mtk_dsi_clk_hs_mode(dsi, 1); > > > > return 0; > > err_disable_engine_clk: > > @@ -769,30 +786,12 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi) > > dsi->lanes_ready =3D false; > > } > > > > -static void mtk_dsi_lane_ready(struct mtk_dsi *dsi) > > -{ > > - if (!dsi->lanes_ready) { > > - dsi->lanes_ready =3D true; > > - mtk_dsi_rxtx_control(dsi); > > - usleep_range(30, 100); > > - mtk_dsi_reset_dphy(dsi); > > - mtk_dsi_clk_ulp_mode_leave(dsi); > > - mtk_dsi_lane0_ulp_mode_leave(dsi); > > - mtk_dsi_clk_hs_mode(dsi, 0); > > - usleep_range(1000, 3000); > > - /* The reaction time after pulling up the mipi signal f= or dsi_rx */ > > - } > > -} > > - > > static void mtk_output_dsi_enable(struct mtk_dsi *dsi) > > { > > if (dsi->enabled) > > return; > > > > - mtk_dsi_lane_ready(dsi); > > mtk_dsi_set_mode(dsi); > > - mtk_dsi_clk_hs_mode(dsi, 1); > > - > > mtk_dsi_start(dsi); > > > > dsi->enabled =3D true; > > > > --- > > base-commit: 8f0b4cce4481fb22653697cced8d0d04027cb1e8 > > change-id: 20260120-mtkdsi-29e4c84e7b38 > > > > Best regards, > > -- > > Gary Bisson > > > > > > > ************* MEDIATEK Confidentiality Notice > ******************** > The information contained in this e-mail message (including any > attachments) may be confidential, proprietary, privileged, or otherwise > exempt from disclosure under applicable laws. It is intended to be > conveyed only to the designated recipient(s). Any use, dissemination, > distribution, printing, retaining or copying of this e-mail (including it= s > attachments) by unintended recipient(s) is strictly prohibited and may > be unlawful. If you are not an intended recipient of this e-mail, or beli= eve > > that you have received this e-mail in error, please notify the sender > immediately (by replying to this e-mail), delete any and all copies of > this e-mail (including any attachments) from your system, and do not > disclose the content of this e-mail to any other person. Thank you!