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Thu, 13 Jul 2023 06:25:02 -0700 (PDT) MIME-Version: 1.0 References: <20230704064610.292603-1-xingyu.wu@starfivetech.com> <20230704064610.292603-8-xingyu.wu@starfivetech.com> In-Reply-To: <20230704064610.292603-8-xingyu.wu@starfivetech.com> From: Emil Renner Berthing Date: Thu, 13 Jul 2023 15:24:46 +0200 Message-ID: Subject: Re: [RESEND PATCH v6 7/7] riscv: dts: starfive: jh7110: Add PLL clocks source in SYSCRG node To: Xingyu Wu Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Hal Feng , William Qiu , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 4 Jul 2023 at 08:49, Xingyu Wu wrote: > > Add PLL clocks input from PLL clocks driver in SYSCRG node. > > Reviewed-by: Conor Dooley > Signed-off-by: Xingyu Wu > --- > arch/riscv/boot/dts/starfive/jh7110.dtsi | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi > index 11dd4c9d64b0..cdfd036a0e6c 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi > @@ -452,12 +452,16 @@ syscrg: clock-controller@13020000 { > <&gmac1_rgmii_rxin>, > <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, > <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, > - <&tdm_ext>, <&mclk_ext>; > + <&tdm_ext>, <&mclk_ext>, > + <&pllclk JH7110_CLK_PLL0_OUT>, > + <&pllclk JH7110_CLK_PLL1_OUT>, > + <&pllclk JH7110_CLK_PLL2_OUT>; Once these are updated to <&pll ?> or <&pllclk JH7110_PLLCLK_PLL?_OUT> if you still want to keep the defines: Reviewed-by: Emil Renner Berthing > clock-names = "osc", "gmac1_rmii_refin", > "gmac1_rgmii_rxin", > "i2stx_bclk_ext", "i2stx_lrck_ext", > "i2srx_bclk_ext", "i2srx_lrck_ext", > - "tdm_ext", "mclk_ext"; > + "tdm_ext", "mclk_ext", > + "pll0_out", "pll1_out", "pll2_out"; > #clock-cells = <1>; > #reset-cells = <1>; > }; > -- > 2.25.1 >