From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: ARC-Seal: i=1; a=rsa-sha256; t=1516485076; cv=none; d=google.com; s=arc-20160816; b=dj8vQk1ZX9Vjk5HJDG45CN4m7kcLXIu7TIExQtMMtexbbUqtV8dGE/7BflglR4++h7 W7qojcFokZsMnkjdLp1/p6UCC7aKzK/BhMGrSE5GJv55LUBrZe5bo9oj5619X7mtI5fu iYlEv/6nS44qGtTDwimOooMH4/Lq57EPD5seLJ5UcPQpmvqZ7ypplN/PoEe+yxEpbS0x +aInpbL1vmuPMR8cJKB81SWkeD48YWN/n9jE6NoPJv0eF5LUn/YhJ2fF4x/R3tMEgLQa ZTpR6uxi+/3jKRMU1UpOkJAzQkIZIvcFVyDQE+4w/1p+YHn0/okD3tGIBG7W1eZ/jyYS H0pA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:subject:message-id:date:from:references:in-reply-to :mime-version:dkim-signature:arc-authentication-results; bh=fPkXwxhkDZpDctfrjgb5TcHx5iNyhsv/8qwiIP9svCk=; b=zc4Iomat+pX6eMpNFoCvccW045yxrDcq9tKhokpdb1MkdV89OpuPXBzeHScpduqAIh /zL4l7Ze+FdkUFsHqax7K3bzmcPNxfreMOR98t/vU/ncsw5YYU86qTrobW4sgElTCgx+ spfiXpT+7bXodc6V6vmxSP5dN73bi23LUdy9LexY4WKdhdIwA0N80p1Z+8BGnCAvAokO VtUhhbmyFfmhKISf4G3dqEyIZdxO2bwwFksNqsUOxvIGue6mx6s2fEBsVDioOH8qIx1h 9S1biaR5AQtp4k5Fw0W7VNs2gZYqU+mbWspaFAGNX6qucgI0Gcvsd4wVSejXdKn9BzzZ 5SZw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@uplinklabs.net header.s=google1 header.b=hW+clFvQ; spf=pass (google.com: domain of steven@uplinklabs.net designates 209.85.220.65 as permitted sender) smtp.mailfrom=steven@uplinklabs.net; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=uplinklabs.net Authentication-Results: mx.google.com; dkim=pass header.i=@uplinklabs.net header.s=google1 header.b=hW+clFvQ; spf=pass (google.com: domain of steven@uplinklabs.net designates 209.85.220.65 as permitted sender) smtp.mailfrom=steven@uplinklabs.net; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=uplinklabs.net X-Google-Smtp-Source: AH8x225H93fDT23T1VUytgDyobLGmD++31UvQdPC7cmVD5OmL+y8UQilQKKh9EbPJ4Ov28fEr3K4kyuNOQBSl5JAn50= MIME-Version: 1.0 In-Reply-To: <1516449813-7654-2-git-send-email-dwmw@amazon.co.uk> References: <1516449813-7654-1-git-send-email-dwmw@amazon.co.uk> <1516449813-7654-2-git-send-email-dwmw@amazon.co.uk> From: Steven Noonan Date: Sat, 20 Jan 2018 13:51:14 -0800 Message-ID: Subject: Re: [PATCH 1/4] x86/cpufeatures: Add Intel feature bits for Speculation Control To: David Woodhouse Cc: Arjan van de Ven , Thomas Gleixner , karahmed@amazon.de, Linux-X86 , Linux Kernel mailing List , tim.c.chen@linux.intel.com, Borislav Petkov , Peter Zijlstra , Paolo Bonzini , ak@linux.intel.com, Linus Torvalds , gregkh@linux-foundation.org Content-Type: text/plain; charset="UTF-8" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590114213169258479?= X-GMAIL-MSGID: =?utf-8?q?1590149855035645307?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: On Sat, Jan 20, 2018 at 4:03 AM, David Woodhouse wrote: > Add three feature bits exposed by new microcode on Intel CPUs for > speculation control. We would now be up to five bits in CPUID(7).RDX > so take them out of the 'scattered' features and make a proper word > for them instead. > > Signed-off-by: David Woodhouse > --- > arch/x86/include/asm/cpufeature.h | 7 +++++-- > arch/x86/include/asm/cpufeatures.h | 12 +++++++++--- > arch/x86/include/asm/disabled-features.h | 3 ++- > arch/x86/include/asm/required-features.h | 3 ++- > arch/x86/kernel/cpu/common.c | 1 + > arch/x86/kernel/cpu/scattered.c | 2 -- > 6 files changed, 19 insertions(+), 9 deletions(-) > > diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h > index ea9a7dd..70eddb3 100644 > --- a/arch/x86/include/asm/cpufeature.h > +++ b/arch/x86/include/asm/cpufeature.h > @@ -29,6 +29,7 @@ enum cpuid_leafs > CPUID_8000_000A_EDX, > CPUID_7_ECX, > CPUID_8000_0007_EBX, > + CPUID_7_EDX, > }; > > #ifdef CONFIG_X86_FEATURE_NAMES > @@ -79,8 +80,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; > CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 15, feature_bit) || \ > CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 16, feature_bit) || \ > CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 17, feature_bit) || \ > + CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 18, feature_bit) || \ > REQUIRED_MASK_CHECK || \ > - BUILD_BUG_ON_ZERO(NCAPINTS != 18)) > + BUILD_BUG_ON_ZERO(NCAPINTS != 19)) > > #define DISABLED_MASK_BIT_SET(feature_bit) \ > ( CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 0, feature_bit) || \ > @@ -101,8 +103,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; > CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 15, feature_bit) || \ > CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 16, feature_bit) || \ > CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 17, feature_bit) || \ > + CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 18, feature_bit) || \ > DISABLED_MASK_CHECK || \ > - BUILD_BUG_ON_ZERO(NCAPINTS != 18)) > + BUILD_BUG_ON_ZERO(NCAPINTS != 19)) > > #define cpu_has(c, bit) \ > (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index 25b9375..adebdaa 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -13,7 +13,7 @@ > /* > * Defines x86 CPU feature bits > */ > -#define NCAPINTS 18 /* N 32-bit words worth of info */ > +#define NCAPINTS 19 /* N 32-bit words worth of info */ > #define NBUGINTS 1 /* N 32-bit bug flags */ > > /* > @@ -206,8 +206,6 @@ > #define X86_FEATURE_RETPOLINE ( 7*32+12) /* Generic Retpoline mitigation for Spectre variant 2 */ > #define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* AMD Retpoline mitigation for Spectre variant 2 */ > #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */ > -#define X86_FEATURE_AVX512_4VNNIW ( 7*32+16) /* AVX-512 Neural Network Instructions */ > -#define X86_FEATURE_AVX512_4FMAPS ( 7*32+17) /* AVX-512 Multiply Accumulation Single precision */ > > #define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */ > #define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* Fill RSB on context switches */ > @@ -319,6 +317,14 @@ > #define X86_FEATURE_SUCCOR (17*32+ 1) /* Uncorrectable error containment and recovery */ > #define X86_FEATURE_SMCA (17*32+ 3) /* Scalable MCA */ > > +/* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */ > +#define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */ > +#define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */ > +#define X86_FEATURE_SPEC_CTRL (18*32+26) /* Speculation Control (IBRS + IBPB) */ > +#define X86_FEATURE_STIPB (18*32+27) /* Speculation Control with STIPB (Intel) */ Is this correct? I thought the acronym was "STIBP", i.e. "Single-Thread Indrect Branch Prediction"? If so, then you've got the B and P swapped. > +#define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */ > + > + > /* > * BUG word(s) > */ > diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h > index e428e16..c6a3af1 100644 > --- a/arch/x86/include/asm/disabled-features.h > +++ b/arch/x86/include/asm/disabled-features.h > @@ -71,6 +71,7 @@ > #define DISABLED_MASK15 0 > #define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57) > #define DISABLED_MASK17 0 > -#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18) > +#define DISABLED_MASK18 0 > +#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19) > > #endif /* _ASM_X86_DISABLED_FEATURES_H */ > diff --git a/arch/x86/include/asm/required-features.h b/arch/x86/include/asm/required-features.h > index d91ba04..fb3a6de 100644 > --- a/arch/x86/include/asm/required-features.h > +++ b/arch/x86/include/asm/required-features.h > @@ -106,6 +106,7 @@ > #define REQUIRED_MASK15 0 > #define REQUIRED_MASK16 (NEED_LA57) > #define REQUIRED_MASK17 0 > -#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18) > +#define REQUIRED_MASK18 0 > +#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19) > > #endif /* _ASM_X86_REQUIRED_FEATURES_H */ > diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c > index 372ba3f..e5d66e9 100644 > --- a/arch/x86/kernel/cpu/common.c > +++ b/arch/x86/kernel/cpu/common.c > @@ -745,6 +745,7 @@ void get_cpu_cap(struct cpuinfo_x86 *c) > cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); > c->x86_capability[CPUID_7_0_EBX] = ebx; > c->x86_capability[CPUID_7_ECX] = ecx; > + c->x86_capability[CPUID_7_EDX] = edx; > } > > /* Extended state features: level 0x0000000d */ > diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c > index d0e6976..df11f5d 100644 > --- a/arch/x86/kernel/cpu/scattered.c > +++ b/arch/x86/kernel/cpu/scattered.c > @@ -21,8 +21,6 @@ struct cpuid_bit { > static const struct cpuid_bit cpuid_bits[] = { > { X86_FEATURE_APERFMPERF, CPUID_ECX, 0, 0x00000006, 0 }, > { X86_FEATURE_EPB, CPUID_ECX, 3, 0x00000006, 0 }, > - { X86_FEATURE_AVX512_4VNNIW, CPUID_EDX, 2, 0x00000007, 0 }, > - { X86_FEATURE_AVX512_4FMAPS, CPUID_EDX, 3, 0x00000007, 0 }, > { X86_FEATURE_CAT_L3, CPUID_EBX, 1, 0x00000010, 0 }, > { X86_FEATURE_CAT_L2, CPUID_EBX, 2, 0x00000010, 0 }, > { X86_FEATURE_CDP_L3, CPUID_ECX, 2, 0x00000010, 1 }, > -- > 2.7.4 >