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Wed, 28 Oct 2026 14:50:24 -0700 (PDT) X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 References: <20260827223755.143247-1-zide.chen@intel.com> <20260827223755.143247-15-zide.chen@intel.com> In-Reply-To: <20260827223755.143247-15-zide.chen@intel.com> From: Jim Mattson Date: Wed, 28 Oct 2026 14:50:09 -0700 X-Gm-Features: AclHuK-liHGzIvCMjGYc6qSRUa3UjMY3TGndjwxwFoPElrqbY_zUPbSfw_KI05g Message-ID: Subject: Re: [PATCH v2 14/16] KVM: x86/pmu: Ignore AnyThread bit if CPUID.0AH:EDX[15] is set To: Zide Chen Cc: Sean Christopherson , Paolo Bonzini , Peter Zijlstra , kvm@vger.kernel.org, Andi Kleen , Stephane Eranian , linux-kernel@vger.kernel.org, Mingwei Zhang , Das Sandipan , Shukla Manali , Dapeng Mi , Xudong Hao Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Aug 27, 2026 at 3:48=E2=80=AFPM Zide Chen wro= te: > > Intel PerfMon v5 introduces the ANYTHREAD_DEPRECATION capability > (CPUID.0AH:EDX[15]) to indicate that AnyThread counting is deprecated > and that writes to the AnyThread bit in IA32_PERFEVTSELx are ignored. > > When ANYTHREAD_DEPRECATION is present in the guest CPUID, emulate the > architectural behavior and silently ignore writes to the AnyThread bit > instead of injecting #GP. > > Continue to inject #GP when ANYTHREAD_DEPRECATION is not present in the > guest CPUID, e.g. for PerfMon v3/v4 guests or when the capability is > not configured for a PerfMon v5+ guest. > > Advertise CPUID.0AH:EDX[15] only for PMU version 5+ guests, since the > bit doesn't exist below version 5. > > Signed-off-by: Zide Chen > --- > v2: > - Advertise anythread_deprecated only if kvm_pmu_cap.version >=3D 5. > - Add the missing AnyThr bit handling for IA32_FIXED_CTR_CTRL. > - Update the comments to be clearer. > --- > arch/x86/kvm/cpuid.c | 2 +- > arch/x86/kvm/vmx/pmu_intel.c | 19 +++++++++++++++++++ > 2 files changed, 20 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c > index 63201d4ea4a1..ef208906b3ee 100644 > --- a/arch/x86/kvm/cpuid.c > +++ b/arch/x86/kvm/cpuid.c > @@ -1542,7 +1542,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_= array *array, u32 function) > KVM_MAX_NR_FIXED_COUNTERS); > edx.split.bit_width_fixed =3D kvm_pmu_cap.bit_width_fixed= ; > > - if (kvm_pmu_cap.version) > + if (kvm_pmu_cap.version >=3D 5) > edx.split.anythread_deprecated =3D 1; > > entry->eax =3D eax.full; > diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c > index c7472778137a..599c69dfa6e3 100644 > --- a/arch/x86/kvm/vmx/pmu_intel.c > +++ b/arch/x86/kvm/vmx/pmu_intel.c > @@ -446,6 +446,12 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, = struct msr_data *msr_info) > if (data & pmu->fixed_ctr_ctrl_rsvd) > return 1; > > + /* > + * This is to emulate ANYTHREAD_DEPRECATION. Guests witho= ut > + * support for it would have had the write rejected by > + * pmu->fixed_ctr_ctrl_rsvd above. > + */ > + data &=3D ~intel_pmu_fixed_ctrl_bits(pmu, INTEL_FIXED_0_A= NYTHREAD); > if (pmu->fixed_ctr_ctrl !=3D data) > reprogram_fixed_counters(pmu, data); > break; > @@ -494,6 +500,8 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, s= truct msr_data *msr_info) > if (data & eventsel_rsvd) > return 1; > > + /* See above comments for MSR_CORE_PERF_FIXED_CTR= _CTRL. */ > + data &=3D ~ARCH_PERFMON_EVENTSEL_ANY; > if (data !=3D pmc->eventsel) { > pmc->eventsel =3D data; > pmc->eventsel_hw =3D data; > @@ -603,6 +611,17 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) > pmu->pmc_exists64 =3D (BIT_ULL(nr_gp_counters) - 1) & > kvm_pmu_cap.cntr_mask64; > > + /* > + * AnyThread counting is not supported by KVM due to cross-VM > + * information leakage concerns on SMT cores. Therefore, AnyThrea= d > + * remains unavailable for PerfMon v3/v4 guests, where AnyThread > + * deprecation is not enumerated. > + */ > + if (pmu->version >=3D 5 && edx.split.anythread_deprecated) { > + pmu->eventsel_rsvd &=3D ~ARCH_PERFMON_EVENTSEL_ANY; > + fixed_enable_bits |=3D INTEL_FIXED_0_ANYTHREAD; > + } > + According to Intel SDM Vol. 4, Table 2-2 ("IA-32 Architectural MSRs"), only Fixed Counters 0, 1, and 2 have an AnyThread bit (bits 2, 6, and 10 of IA32_FIXED_CTR_CTRL). FC3 has never had an AnyThread bit; IA32_FIXED_CTR_CTR[bit 14] is reserved in PerfMon v5 and becomes METRICS_CLEAR_EN in PerfMon v6. Passing INTEL_FIXED_0_ANYTHREAD to intel_pmu_fixed_ctrl_bits() will wrongly clear bit 14 in pmu->fixed_ctr_ctrl_rsvd once Fixed Counter 3 is enabled. On hardware with CPUID.0AH:EDX.ANYTHREAD_DEPRECATION[15] =3D 1, if software sets the AnyThread bit in IA32_PERFEVTSELx or IA32_FIXED_CTR_CTRL and then reads the MSR back with RDMSR, does hardware return 0 for the AnyThread bit, or does it return 1 but otherwise ignore the bit?