From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7AA03C38145 for ; Wed, 7 Sep 2022 16:33:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230134AbiIGQda (ORCPT ); Wed, 7 Sep 2022 12:33:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58422 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229459AbiIGQd0 (ORCPT ); Wed, 7 Sep 2022 12:33:26 -0400 Received: from mail-oa1-x36.google.com (mail-oa1-x36.google.com [IPv6:2001:4860:4864:20::36]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD9E1A7A8A for ; Wed, 7 Sep 2022 09:33:24 -0700 (PDT) Received: by mail-oa1-x36.google.com with SMTP id 586e51a60fabf-127d10b4f19so11607093fac.9 for ; Wed, 07 Sep 2022 09:33:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date; bh=EmmUroBnQkKtzSpVrUefA2RMcw7wGhyCwtTDIpKDhrk=; b=PknB9Wzlt1y0TbVGAQBs/L0GjuCa+I/M92/+1rXq+zMC0AfruyxAtxyXEcTrEW3Vir cA9HDVdlT3akhMsuiWIl4IkuaARR47abE+oak4c84rqaZ6Wqm954cE3zE5Dt/cB169lY d0+OfeBlFYvDD9SMqAnejNpB/yNOlyzgUkk2vdcPPpLVh8hRhYmWS3Hgc+MvxSVKawT2 vcTRd/hlqclFLK+91YwLOBcYjJ8WQiIkc9b5GDImrPRgLDTWzvuLrvyhXtsdHMta1RxV x6pnLBQUEkh0tTGjcjzOnB15ruIEkZDQPywrjHEsfW1sajwj/lIre/0Vr2JJ5CaiCpE5 nodg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date; bh=EmmUroBnQkKtzSpVrUefA2RMcw7wGhyCwtTDIpKDhrk=; b=xcBP3zmTtgbgop+lD6LPuCoSW7/iS4DrXulD8uKGLx+gnj/DqR2otC9C4jkHdvIfEG uUsfRBFheTig0g5jk7J/s4THEwE1yYOZkofkz1P4JDb1UD8R0w8R3+na41X90M42I5b+ OWyoEWm635u+F/xnXFdSb960zHak2DrqOOpznJIv2VIs48mFCrvOgsMuqyP+NZD88SQI 6azgG+fY4TicSMkUk2w5TohzuPKNEKOpspsiRjeBiPT/JCf+NKRJBCyHsukmHnGphsM0 rxI2oFycFGp3vkb4PF4E3Y5oh4EmIqU/9Qa1OJFP1+yXYvhtibKtf55HqG+9dvzwfOka W4Xw== X-Gm-Message-State: ACgBeo3BD7wSlutMba36OdGOyq6N5PAtlH6f5go+t6LVoJrklfWa5lj3 H7sR5v+XsG0058hUdVcY2wlWA7ak7h1U4eHoaKW+Lw== X-Google-Smtp-Source: AA6agR4kzdBfcMicmpDRKNagmkro3jVBoG3aMKLRx/kY02XEbylzC5Z20E/hkkos05UKSPVjscEoWuqIuFX1v8fHD9I= X-Received: by 2002:a05:6870:41d0:b0:126:5d06:28a5 with SMTP id z16-20020a05687041d000b001265d0628a5mr2299318oac.181.1662568403992; Wed, 07 Sep 2022 09:33:23 -0700 (PDT) MIME-Version: 1.0 References: <20220907104838.8424-1-likexu@tencent.com> In-Reply-To: <20220907104838.8424-1-likexu@tencent.com> From: Jim Mattson Date: Wed, 7 Sep 2022 09:33:13 -0700 Message-ID: Subject: Re: [PATCH v2 1/3] KVM: x86/pmu: Stop adding speculative Intel GP PMCs that don't exist yet To: Like Xu Cc: Sean Christopherson , Paolo Bonzini , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Vitaly Kuznetsov Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Sep 7, 2022 at 3:48 AM Like Xu wrote: > > From: Like Xu > > The Intel April 2022 SDM - Table 2-2. IA-32 Architectural MSRs adds > a new architectural IA32_OVERCLOCKING_STATUS msr (0x195), plus the > presence of IA32_CORE_CAPABILITIES (0xCF), the theoretical effective > maximum value of the Intel GP PMCs is 14 (0xCF - 0xC1) instead of 18. > > But the conclusion of this speculation "14" is very fragile and can > easily be overturned once Intel declares another meaningful arch msr > in the above reserved range, and even worse, Intel probably put PMCs > 8-15 in a completely different range of MSR indices. The last clause is just conjecture. > A conservative proposal would be to stop at the maximum number of Intel > GP PMCs supported today. Also subsequent changes would limit both AMD > and Intel on the number of GP counter supported by KVM. > > There are some boxes like Intel P4 may indeed have 18 counters, but > those counters are in a completely different msr address range and do > not strictly adhere to the Intel Arch PMU specification, and will not > be supported by KVM in the near future. The P4 PMU isn't virtualized by KVM today, is it? > > Cc: Vitaly Kuznetsov > Suggested-by: Jim Mattson > Signed-off-by: Like Xu Please put the "Fixes" tag back. You convinced me that it should be there. Reviewed-by: Jim Mattson