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AJvYcCUwqg38+Fudt/rSV0/h4iRSsKxrZAjcmfFVRWY0MRyi+Qg5KgdHszSGqAWnktvQ856k1S86toPAzBxUDSs=@vger.kernel.org X-Gm-Message-State: AOJu0YywpPKRu++0H7Gok3NFvoSabfK8fTRTJv5+4tyniBzbZYUo0gi+ HRfkGbEu0BUq7wFT/A2TuHGIrSKcsjFTMRaXmU00ADmeZMQGSMlJCYLWtSpormwh43iujb872wQ fvIM/iJqdHQZkeDYCkqwbzf0qC9LZGHAEKNHWb+uK X-Gm-Gg: AeBDietDKdzM+efzIxDJcZOAXcQKn9nlg8AtgdwPQYmHqQSTnVSEGgN/yGAnp1ICy+n Ab8qG04NeEAwuH3PDjtBqcPY4s08RLWheGNNXZh9fWzJXljxv3/lSoIrweVuEtBdTtGr7KeJ4mq +cMOoxajBgZY68/fkaY6qaSk4D6N04tNjs5bUluMu1I65sAWm4yWEzAvdHWcednbhJrD817o2P2 v3xoA+RtRls+FDn/vdEyRpzYSUdbWI1G2N8t8cg/x0q8PXnDb0Zt3cRQ6Q4bG2IfkBcEz6GD0UG /+JUPD0= X-Received: by 2002:a05:6402:5192:b0:66b:b6d8:c0f7 with SMTP id 4fb4d7f45d1cf-66f9e8a747amr784a12.0.1775595221201; Tue, 07 Apr 2026 13:53:41 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20260403233329.fb2ppifgwm3um6ny@desk> <20260404002149.wtayv6a64vzuppgp@desk> <20260404034954.t7iapenzvhdpagxp@desk> <20260407163943.y6tkh26z2rfktn3y@desk> <20260407171151.2gf2idjbmph35ypb@desk> <20260407191128.b2hr2ttkdpyunhrr@desk> In-Reply-To: <20260407191128.b2hr2ttkdpyunhrr@desk> From: Jim Mattson Date: Tue, 7 Apr 2026 13:53:24 -0700 X-Gm-Features: AQROBzDTwGQS7R5PAsEU3h53Sr6ks4a8QPBLHblMF9o5FM5amaSGtHZz6ABr9Kk Message-ID: Subject: Re: [PATCH v9 02/10] x86/bhi: Make clear_bhb_loop() effective on newer CPUs To: Pawan Gupta Cc: x86@kernel.org, Jon Kohler , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet , linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org, chao.gao@intel.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, Apr 7, 2026 at 12:11=E2=80=AFPM Pawan Gupta wrote: > > On Tue, Apr 07, 2026 at 11:40:57AM -0700, Jim Mattson wrote: > > My proposal is as follows: > > > > 1. The (advanced) hypervisor can advertise to the guest (via CPUID bit > > or MSR bit) that the short BHB clearing sequence is adequate. This may > > mean either that the VM will only be hosted on pre-Alder Lake hardware > > or that the hypervisor will set BHI_DIS_S behind the back of the > > guest. Presumably, this bit would not be reported if BHI_CTRL is > > advertised to the guest. > > 2. If the guest sees this bit, then it can use the short sequence. If > > it doesn't see this bit, it must use the long sequence. > > Thats a good middle ground. Let me check with folks internally what they > think about defining a new software-only bit. > > Third case, for a guest that doesn't want BHI_DIS_S, userspace should be > allowed to override setting BHI_DIS_S. Then this proposed bit can indicat= e > that long sequence is required. That case can be handled by the paravirtual mitigation MSRs, right?