From: Bartosz Golaszewski <brgl@kernel.org>
To: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com>
Cc: Alberto Ruiz <aruizrui@redhat.com>,
Christophe Lizzi <clizzi@redhat.com>,
devicetree@vger.kernel.org, Enric Balletbo <eballetb@redhat.com>,
Eric Chanudet <echanude@redhat.com>,
imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org,
NXP S32 Linux Team <s32@nxp.com>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Vincent Guittot <vincent.guittot@linaro.org>,
Linus Walleij <linusw@kernel.org>,
Bartosz Golaszewski <brgl@bgdev.pl>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Chester Lin <chester62515@gmail.com>,
Matthias Brugger <mbrugger@suse.com>,
Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>,
Larisa Grigore <larisa.grigore@nxp.com>,
Lee Jones <lee@kernel.org>, Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>,
Dong Aisheng <aisheng.dong@nxp.com>,
Jacky Bai <ping.bai@nxp.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Srinivas Kandagatla <srini@kernel.org>
Subject: Re: [PATCH v12 6/6] arm64: dts: s32g: describe GPIO and EIRQ resources in SIUL2 pinctrl node
Date: Wed, 1 Jul 2026 03:50:23 -0400 [thread overview]
Message-ID: <CAMRc=MfQDX7qNzmYP99RqvYtwVa9KsxKu4qq+8TD5Vz5FvrKOg@mail.gmail.com> (raw)
In-Reply-To: <20260630125403.546375-7-khristineandreea.barbulescu@oss.nxp.com>
On Tue, 30 Jun 2026 14:54:03 +0200, Khristine Andreea Barbulescu
<khristineandreea.barbulescu@oss.nxp.com> said:
> Update the SIUL2 pinctrl node to describe the additional register
> ranges and DT properties used by the updated SIUL2 driver.
>
> Besides the MSCR and IMCR ranges used for pinmux and pin
> configuration, the SIUL2 block also provides PGPDO and
> PGPDI registers for GPIO output and input operations,
> as well as an EIRQ register window for external interrupt configuration.
>
> The driver supports both legacy pinctrl-only DTs and
> extended DTs with GPIO and IRQ.
>
> Reflect these resources in the SIUL2 pinctrl node by adding:
> - the PGPDO and PGPDI register ranges
> - the EIRQ register range
> - gpio-controller, #gpio-cells and gpio-ranges
> - interrupt-controller, #interrupt-cells and interrupts
>
> Keep the hardware description aligned with the updated SIUL2
> driver, where pinctrl, GPIO data access and the EIRQ register
> block are described under the same device node.
>
> Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com>
> ---
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
next prev parent reply other threads:[~2026-07-01 7:50 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-30 12:53 [PATCH v12 0/6] gpio: siul2-s32g2: add initial GPIO driver Khristine Andreea Barbulescu
2026-06-30 12:53 ` [PATCH v12 1/6] pinctrl: s32cc: add/fix some comments Khristine Andreea Barbulescu
2026-06-30 15:24 ` Frank Li
2026-06-30 12:53 ` [PATCH v12 2/6] pinctrl: s32cc: remove inline specifiers Khristine Andreea Barbulescu
2026-06-30 15:22 ` Frank Li
2026-06-30 12:54 ` [PATCH v12 3/6] pinctrl: s32cc: change to "devm_pinctrl_register_and_init" Khristine Andreea Barbulescu
2026-06-30 12:54 ` [PATCH v12 4/6] dt-bindings: pinctrl: s32g2-siul2: describe GPIO and EIRQ resources Khristine Andreea Barbulescu
2026-07-01 7:47 ` Bartosz Golaszewski
2026-06-30 12:54 ` [PATCH v12 5/6] pinctrl: s32cc: implement GPIO functionality Khristine Andreea Barbulescu
2026-07-01 7:50 ` Bartosz Golaszewski
2026-06-30 12:54 ` [PATCH v12 6/6] arm64: dts: s32g: describe GPIO and EIRQ resources in SIUL2 pinctrl node Khristine Andreea Barbulescu
2026-07-01 7:50 ` Bartosz Golaszewski [this message]
2026-07-01 10:28 ` [PATCH v12 0/6] gpio: siul2-s32g2: add initial GPIO driver Linus Walleij
2026-07-06 16:02 ` (subset) " Frank.Li
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAMRc=MfQDX7qNzmYP99RqvYtwVa9KsxKu4qq+8TD5Vz5FvrKOg@mail.gmail.com' \
--to=brgl@kernel.org \
--cc=aisheng.dong@nxp.com \
--cc=aruizrui@redhat.com \
--cc=brgl@bgdev.pl \
--cc=chester62515@gmail.com \
--cc=clizzi@redhat.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=eballetb@redhat.com \
--cc=echanude@redhat.com \
--cc=festevam@gmail.com \
--cc=ghennadi.procopciuc@nxp.com \
--cc=gregkh@linuxfoundation.org \
--cc=imx@lists.linux.dev \
--cc=kernel@pengutronix.de \
--cc=khristineandreea.barbulescu@oss.nxp.com \
--cc=krzk+dt@kernel.org \
--cc=larisa.grigore@nxp.com \
--cc=lee@kernel.org \
--cc=linusw@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-gpio@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mbrugger@suse.com \
--cc=ping.bai@nxp.com \
--cc=rafael@kernel.org \
--cc=robh@kernel.org \
--cc=s.hauer@pengutronix.de \
--cc=s32@nxp.com \
--cc=shawnguo@kernel.org \
--cc=srini@kernel.org \
--cc=vincent.guittot@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox