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[209.85.217.52]) by smtp.gmail.com with ESMTPSA id 71dfb90a1353d-557bdbbba23sm506135e0c.13.2025.10.23.00.55.36 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 23 Oct 2025 00:55:36 -0700 (PDT) Received: by mail-vs1-f52.google.com with SMTP id ada2fe7eead31-5db30731362so352727137.3 for ; Thu, 23 Oct 2025 00:55:36 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCXiTj5aMA6mQGClSmWx9jVPPVDbTMtp+iPXu5WqtN7Ifo0bk02ArDC3ExBX5hFbthCFS6ipOSwzCNiabw4=@vger.kernel.org X-Received: by 2002:a05:6102:38cb:b0:5db:337d:65c6 with SMTP id ada2fe7eead31-5db337d6988mr173700137.23.1761206136224; Thu, 23 Oct 2025 00:55:36 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20251007133657.390523-3-claudiu.beznea.uj@bp.renesas.com> <20251022194939.GA1223383@bhelgaas> In-Reply-To: <20251022194939.GA1223383@bhelgaas> From: Geert Uytterhoeven Date: Thu, 23 Oct 2025 09:55:25 +0200 X-Gmail-Original-Message-ID: X-Gm-Features: AS18NWCwdsxUw7zogPqVrxEDzYqaWGHMFOcHzYZ5pvVfO4qa6VaOrBUa-VfGcUI Message-ID: Subject: Re: [PATCH v5 2/6] PCI: rzg3s-host: Add Renesas RZ/G3S SoC host driver To: Bjorn Helgaas Cc: Claudiu , lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, bhelgaas@google.com, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com, p.zabel@pengutronix.de, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea , Wolfram Sang Content-Type: text/plain; charset="UTF-8" Hi Bjorn, On Wed, 22 Oct 2025 at 21:49, Bjorn Helgaas wrote: > On Tue, Oct 07, 2025 at 04:36:53PM +0300, Claudiu wrote: > > From: Claudiu Beznea > > > > The Renesas RZ/G3S features a PCIe IP that complies with the PCI Express > > Base Specification 4.0 and supports speeds of up to 5 GT/s. It functions > > only as a root complex, with a single-lane (x1) configuration. The > > controller includes Type 1 configuration registers, as well as IP > > specific registers (called AXI registers) required for various adjustments. > > +++ b/drivers/pci/controller/pcie-rzg3s-host.c > > > +#define RZG3S_PCI_MSIRCVWMSKL 0x108 > > +#define RZG3S_PCI_MSIRCVWMSKL_MASK GENMASK(31, 2) > > Unfortunate to have to add _MASK here when none of the other GENMASKs Actually the unused RZG3S_PCI_MSIRCVWMSKU below would need one, too: #define RZG3S_PCI_MSIRCVWMSKU_MASK GENMASK(30, 0) > need it. Can't think of a better name though. MASK is a good name, as the register bits actually specify (part of) the window mask. > > > +#define RZG3S_PCI_MSIRCVWMSKU 0x10c > > Unused. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds