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[209.85.217.44]) by smtp.gmail.com with ESMTPSA id 71dfb90a1353d-56a91bbd85csm5538855e0c.7.2026.02.27.00.20.21 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 27 Feb 2026 00:20:21 -0800 (PST) Received: by mail-vs1-f44.google.com with SMTP id ada2fe7eead31-5ff10630b18so555335137.3 for ; Fri, 27 Feb 2026 00:20:21 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCURNy7/0mL+X6ebtOwQEGtz/0cqQZsVsBU5IGNUFxK7mnGlr8qvounx1fowbzMO7RQLbhTLIg/eGFhwg90=@vger.kernel.org X-Received: by 2002:a05:6102:b0f:b0:5f0:2451:5f5 with SMTP id ada2fe7eead31-5ff3227b5fdmr919932137.7.1772180420917; Fri, 27 Feb 2026 00:20:20 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20260226-clk-det-rate-fw-managed-v1-0-4421dd2f6dc6@redhat.com> <20260226-clk-det-rate-fw-managed-v1-11-4421dd2f6dc6@redhat.com> In-Reply-To: <20260226-clk-det-rate-fw-managed-v1-11-4421dd2f6dc6@redhat.com> From: Geert Uytterhoeven Date: Fri, 27 Feb 2026 09:20:09 +0100 X-Gmail-Original-Message-ID: X-Gm-Features: AaiRm514zxc-j2wSE9hmPrV4K28ncYIEZUw_Gwmc4uNdGcUAjx-4leTB7pDypQg Message-ID: Subject: Re: [PATCH 11/13] clk: renesas: rzg2l-cpg: drop determine_rate op and use CLK_ROUNDING_FW_MANAGED flag To: Brian Masney Cc: Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Content-Type: text/plain; charset="UTF-8" Hi Brian, C Biju On Thu, 26 Feb 2026 at 19:18, Brian Masney wrote: > This clk driver has a noop determine_rate clk op. Drop this empty > function, and enable the CLK_ROUNDING_FW_MANAGED flag. > > Signed-off-by: Brian Masney Thanks for your patch! > --- a/drivers/clk/renesas/rzg2l-cpg.c > +++ b/drivers/clk/renesas/rzg2l-cpg.c > @@ -938,12 +938,6 @@ static unsigned long rzg2l_cpg_sipll5_recalc_rate(struct clk_hw *hw, > return pll5_rate; > } > > -static int rzg2l_cpg_sipll5_determine_rate(struct clk_hw *hw, > - struct clk_rate_request *req) > -{ > - return 0; > -} > - > static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw, > unsigned long rate, > unsigned long parent_rate) > @@ -1015,7 +1009,6 @@ static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw, > > static const struct clk_ops rzg2l_cpg_sipll5_ops = { > .recalc_rate = rzg2l_cpg_sipll5_recalc_rate, > - .determine_rate = rzg2l_cpg_sipll5_determine_rate, > .set_rate = rzg2l_cpg_sipll5_set_rate, > }; > > @@ -1041,7 +1034,7 @@ rzg2l_cpg_sipll5_register(const struct cpg_core_clk *core, > init.name = core->name; > parent_name = __clk_get_name(parent); > init.ops = &rzg2l_cpg_sipll5_ops; > - init.flags = 0; > + init.flags = CLK_ROUNDING_FW_MANAGED; Iff this is the Right Thing To Do (TM), it needs a comment, as this clock is not managed by firmware. > init.parent_names = &parent_name; > init.num_parents = 1; > Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds