From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Prabhakar <prabhakar.csengg@gmail.com>
Cc: Andrzej Hajda <andrzej.hajda@intel.com>,
Neil Armstrong <neil.armstrong@linaro.org>,
Robert Foss <rfoss@kernel.org>,
Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
Jonas Karlman <jonas@kwiboo.se>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
David Airlie <airlied@gmail.com>,
Simona Vetter <simona@ffwll.ch>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Biju Das <biju.das.jz@bp.renesas.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Magnus Damm <magnus.damm@gmail.com>,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
linux-clk@vger.kernel.org,
Fabrizio Castro <fabrizio.castro.jz@renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v3 10/15] drm: renesas: rz-du: mipi_dsi: Use mHz for D-PHY frequency calculations
Date: Tue, 22 Apr 2025 09:41:07 +0200 [thread overview]
Message-ID: <CAMuHMdWs7R9rtS7Ur6PP9e3m9ghkM1jc_Xn3QOWG4rvTtB2omA@mail.gmail.com> (raw)
In-Reply-To: <20250418184658.456398-11-prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi Prabhakar,
On Fri, 18 Apr 2025 at 20:47, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Pass the HSFREQ in milli-Hz to the `dphy_init()` callback to improve
> precision, especially for the RZ/V2H(P) SoC, where PLL dividers require
> high accuracy.
>
> These changes prepare the driver for upcoming RZ/V2H(P) SoC support.
>
> Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v2->v3:
> - Replaced `unsigned long long` with `u64`
> - Replaced *_mhz with *_millihz` in functions
Thanks for the update!
> @@ -203,8 +203,9 @@ static u32 rzg2l_mipi_dsi_link_read(struct rzg2l_mipi_dsi *dsi, u32 reg)
> */
>
> static int rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi *dsi,
> - unsigned long hsfreq)
> + u64 hsfreq_millihz)
> {
> + unsigned long hsfreq = DIV_ROUND_CLOSEST_ULL(hsfreq_millihz, KILO);
MILLI (everywhere)
It's a strange world where KILO == MILLI ;-)
include/linux/units.h:#define KILO 1000UL
include/linux/units.h-#define MILLI 1000UL
> const struct rzg2l_mipi_dsi_timings *dphy_timings;
> unsigned int i;
> u32 dphyctrl0;
> @@ -277,6 +278,7 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi,
> const struct drm_display_mode *mode)
> {
> unsigned long hsfreq, vclk_rate;
> + u64 hsfreq_millihz;
> unsigned int bpp;
> u32 txsetr;
> u32 clstptsetr;
> @@ -305,9 +307,9 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi,
> */
> bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
> vclk_rate = clk_get_rate(dsi->vclk);
> - hsfreq = DIV_ROUND_CLOSEST_ULL(vclk_rate * bpp, dsi->lanes);
> + hsfreq_millihz = DIV_ROUND_CLOSEST_ULL(vclk_rate * bpp * KILO * 1ULL, dsi->lanes);
The "* 1ULL" only makes the last factor unsigned long long.
"vclk_rate * bpp" is still unsigned long, causing overflow on 32-bit.
As there is no rounding variant of mul_u64_u32_div(), you probably
want to use mul_u32_u32() instead.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
next prev parent reply other threads:[~2025-04-22 7:41 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-18 18:46 [PATCH v3 00/15] Add support for DU and DSI on the Renesas RZ/V2H(P) SoC Prabhakar
2025-04-18 18:46 ` [PATCH v3 01/15] clk: renesas: rzv2h-cpg: Add support for DSI clocks Prabhakar
2025-04-18 19:42 ` ALOK TIWARI
2025-04-18 18:46 ` [PATCH v3 02/15] clk: renesas: r9a09g057: Add clock and reset entries for DSI and LCDC Prabhakar
2025-04-18 18:46 ` [PATCH v3 03/15] dt-bindings: display: renesas,rzg2l-du: Add support for RZ/V2H(P) SoC Prabhakar
2025-04-18 18:46 ` [PATCH v3 04/15] dt-bindings: display: bridge: renesas,dsi: " Prabhakar
2025-04-18 18:46 ` [PATCH v3 05/15] drm: renesas: rz-du: " Prabhakar
2025-04-18 18:46 ` [PATCH v3 06/15] drm: renesas: rz-du: mipi_dsi: Add min check for VCLK range Prabhakar
2025-04-18 18:46 ` [PATCH v3 07/15] drm: renesas: rz-du: mipi_dsi: Simplify HSFREQ calculation Prabhakar
2025-04-18 18:46 ` [PATCH v3 08/15] drm: renesas: rz-du: mipi_dsi: Use VCLK for " Prabhakar
2025-04-18 18:46 ` [PATCH v3 09/15] drm: renesas: rz-du: mipi_dsi: Add OF data support Prabhakar
2025-04-18 18:46 ` [PATCH v3 10/15] drm: renesas: rz-du: mipi_dsi: Use mHz for D-PHY frequency calculations Prabhakar
2025-04-22 7:41 ` Geert Uytterhoeven [this message]
2025-04-23 11:53 ` Lad, Prabhakar
2025-04-18 18:46 ` [PATCH v3 11/15] drm: renesas: rz-du: mipi_dsi: Add feature flag for 16BPP support Prabhakar
2025-04-18 18:46 ` [PATCH v3 12/15] drm: renesas: rz-du: mipi_dsi: Add dphy_late_init() callback for RZ/V2H(P) Prabhakar
2025-04-18 18:46 ` [PATCH v3 13/15] drm: renesas: rz-du: mipi_dsi: Add function pointers for configuring VCLK and mode validation Prabhakar
2025-04-18 18:46 ` [PATCH v3 14/15] drm: renesas: rz-du: mipi_dsi: Add support for LPCLK handling Prabhakar
2025-04-18 18:46 ` [PATCH v3 15/15] drm: renesas: rz-du: mipi_dsi: Add support for RZ/V2H(P) SoC Prabhakar
2025-04-19 7:28 ` Biju Das
2025-04-22 8:32 ` Lad, Prabhakar
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