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[209.85.222.53]) by smtp.gmail.com with ESMTPSA id 71dfb90a1353d-56a91bcc3eesm19480310e0c.8.2026.03.03.06.20.35 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Mar 2026 06:20:36 -0800 (PST) Received: by mail-ua1-f53.google.com with SMTP id a1e0cc1a2514c-94dd01deb53so1294282241.0 for ; Tue, 03 Mar 2026 06:20:35 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCU+ALYuNLEuWmiBrRtTNj3HfUKFDLxRCJEkYcXGP0b2vNg9iqq91HGQlAVJ1F2o0GlQGnU1SsmhJ+9k/9k=@vger.kernel.org X-Received: by 2002:a05:6102:d8f:b0:5fd:ee19:8b30 with SMTP id ada2fe7eead31-5ff3258ba0cmr5792258137.35.1772547635180; Tue, 03 Mar 2026 06:20:35 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20260302135703.162601-1-claudiu.beznea.uj@bp.renesas.com> In-Reply-To: <20260302135703.162601-1-claudiu.beznea.uj@bp.renesas.com> From: Geert Uytterhoeven Date: Tue, 3 Mar 2026 15:20:23 +0100 X-Gmail-Original-Message-ID: X-Gm-Features: AaiRm53qSSjkvTClA8LrrJ8BcCzq-ceTd4NKfpQmi95ie9fBdePR4ZDrlLHB6KU Message-ID: Subject: Re: [PATCH] arm64: dts: renesas: rzg3s-smarc-som: Set bypass for Versa3 PLL2 To: Claudiu Cc: magnus.damm@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, biju.das.jz@bp.renesas.com, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Mon, 2 Mar 2026 at 14:57, Claudiu wrote: > From: Claudiu Beznea > > The default settings for the Versa3 device on the Renesas RZ/G3S SMARC > SoM board have PLL2 disabled. PLL2 was later enabled together with audio > support, as it is required to support both 44.1 kHz and 48 kHz audio. > > With PLL2 enabled, it was observed that Linux occasionally either hangs > during boot (the last log message being related to the I2C probe) or > randomly crashes. This was mainly reproducible on cold boots. During > debugging, it was also noticed that the Unicode replacement character (= =EF=BF=BD) > sometimes appears on the serial console. Further investigation traced thi= s > to the configuration applied through the Versa3 register at offset 0x1c, > which controls PLL enablement. > > The appearance of the Unicode replacement character suggested an issue > with the SoC reference clock. The RZ/G3S reference clock is provided by > the Versa3 clock generator (REF output). > > After checking with the Renesas Versa3 hardware team, it was found that > this is related to the PLL2 lock bit being set through the > renesas,settings DT property. > > The PLL lock bit must be set to avoid unstable clock output from the PLL. > However, due to the Versa3 hardware design, when a PLL lock bit is set, > all outputs (including the REF clock) are temporarily disabled until the > configured PLLs become stable. > > As an alternative, the bypass bit can be used. This does not interrupt th= e > PLL2 output or any other Versa3 outputs, but it may result in temporary > instability on PLL2 output while the configuration is applied. Since PLL2 > feeds only the audio path and audio is not used during early boot, this i= s > acceptable and does not affect system boot. > > Drop the PLL2 lock bit and set the bypass bit instead. > > This has been tested with more than 1000 cold boots. > > Fixes: a94253232b04 ("arm64: dts: renesas: rzg3s-smarc-som: Add versa3 cl= ock generator node") > Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven i.e. will queue in renesas-fixes for v7.0. Gr{oetje,eeting}s, Geert --=20 Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k= .org In personal conversations with technical people, I call myself a hacker. Bu= t when I'm talking to journalists I just say "programmer" or something like t= hat. -- Linus Torvalds