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charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjA1MDA5MSBTYWx0ZWRfXzcIn9byBN55M QUvrtyzX6h3y4RRdl3NNyKUBHhu893Sv46lfnFEKEYGcwoqpZ1yBahrPkMBFYB81zZxcznxDAeh IKdqIF2+YeWq0bpOtb7+I5fUUM9dTmBxLrNqto93/MzZwf0gOhgJbX9SZM194+40JGwIH2m1LbZ Ix2tOzJO383wjHj34MMSIjLSuR80XlFxh8R1OVY9pVcYBnZ/4CoxXc0LJSkgXlXVBxkRY6vNu4u VC3ByN7KrDUX+7BH17Fwg7ueGQ8Evbcwq7yZBJpfLywAyzxNnkxB77YfSHgP1t972LjJjiRYTcU vEY9gCNdb/K4e/1SmhLpezg0NY4nLAAG3KOhjT2XiidT+f1qapSnETUm+NYQW0CQHt6pPm5Kpz/ nD2qhr3qObptuZFDOvq9HPcQvjbp3w== X-Proofpoint-ORIG-GUID: V6ffy6zVuEIebm0dARQ1TdGvOnA3v0G2 X-Proofpoint-GUID: V6ffy6zVuEIebm0dARQ1TdGvOnA3v0G2 X-Authority-Analysis: v=2.4 cv=GtVPO01C c=1 sm=1 tr=0 ts=6932d713 cx=c_pps a=4ztaESFFfuz8Af0l9swBwA==:117 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=gEfo2CItAAAA:8 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=Y2liBin7rq7SVpFgswsA:9 a=QEXdDO2ut3YA:10 a=TPnrazJqx2CeVZ-ItzZ-:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-05_04,2025-12-04_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 adultscore=0 suspectscore=0 impostorscore=0 clxscore=1015 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512050091 On Fri, Dec 5, 2025 at 2:40=E2=80=AFPM Krzysztof Kozlowski wrote: > > On Wed, Dec 03, 2025 at 06:56:47PM +0530, Mrinmay Sarkar wrote: > > Document the required configuration to enable the PCIe Endpoint control= ler > > on SA8255p which is managed by firmware using power-domain based handli= ng. > > > > Signed-off-by: Mrinmay Sarkar > > --- > > .../bindings/pci/qcom,pcie-ep-sa8255p.yaml | 114 +++++++++++++= ++++++++ > > Filename must match the compatible. In your case, the filename is > correct but you wanted old format for the compatible (so compatible > should be rewritten to match filename). Thanks Krzysztof for the review. I will fix the compatible string to match the filename (`qcom,pcie-ep-sa825= 5p`). > > > 1 file changed, 114 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep-sa8255p= .yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep-sa8255p.yaml > > new file mode 100644 > > index 0000000000000000000000000000000000000000..970f65d46c8e2fa4c44665c= b7a346dea1dc9e06a > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep-sa8255p.yaml > > @@ -0,0 +1,114 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/pci/qcom,pcie-ep-sa8255p.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Qualcomm firmware managed PCIe Endpoint Controller > > + > > +description: > > + Qualcomm SA8255p SoC PCIe endpoint controller is based on the Synops= ys > > + DesignWare PCIe IP which is managed by firmware. > > + > > +maintainers: > > + - Manivannan Sadhasivam > > + > > +properties: > > + compatible: > > + const: qcom,sa8255p-pcie-ep > > + > > + reg: > > + minItems: 6 > > Why is this flexible? The reason for `minItems: 6` is that the DMA register space can be skipped if DMA is not used. > > > + items: > > + - description: Qualcomm-specific PARF configuration registers > > + - description: DesignWare PCIe registers > > + - description: External local bus interface registers > > + - description: Address Translation Unit (ATU) registers > > + - description: Memory region used to map remote RC address space > > + - description: BAR memory region > > + - description: DMA register space > > + > > + reg-names: > > + minItems: 6 > > + items: > > + - const: parf > > + - const: dbi > > + - const: elbi > > + - const: atu > > + - const: addr_space > > + - const: mmio > > + - const: dma > > + > > + interrupts: > > + minItems: 2 > > And this/ Similarly, DMA interrupt can be skipped if DMA is not used. > > > + items: > > + - description: PCIe Global interrupt > > + - description: PCIe Doorbell interrupt > > + - description: DMA interrupt > > + > > + interrupt-names: > > + minItems: 2 > > + items: > > + - const: global > > + - const: doorbell > > + - const: dma > > + > > + iommus: > > + maxItems: 1 > > + > > + reset-gpios: > > + description: GPIO used as PERST# input signal > > + maxItems: 1 > > + > > + wake-gpios: > > + description: GPIO used as WAKE# output signal > > + maxItems: 1 > > + > > + power-domains: > > + maxItems: 1 > > + > > + dma-coherent: true > > + > > + num-lanes: > > + default: 2 > > Isn't this deducible from the compatible? Do you have have different > PCIe controllers with different lanes? SA8255p has 2 pcie controllers(pcie0 and pcie1). pcie0 supports 2 lanes, and pcie1 supports 4 lanes. -Mrinmay > > > > + > > +required: > > + - compatible > > + - reg > > + - reg-names > > + - interrupts > > + - interrupt-names > > + - reset-gpios > > + - power-domains > > + > > +additionalProperties: false > > Best regards, > Krzysztof >