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Wed, 20 Aug 2025 07:01:35 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240205171930.968-1-linux.amoon@gmail.com> <20240205171930.968-2-linux.amoon@gmail.com> In-Reply-To: From: Anand Moon Date: Wed, 20 Aug 2025 19:31:16 +0530 X-Gm-Features: Ac12FXyMcTdBuOxtvDWahcqoFUq85wpCJOj43vT1dhbjrrGJIqgkd2zIHaAMyYo Message-ID: Subject: Re: [PATCHv1 1/5] arm64: dts: amlogic: Add cache information to the Amlogic GXBB and GXL SoC To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Hi Neil, On Tue, 27 Feb 2024 at 18:33, Anand Moon wrote: > > Hi Neil, > > On Mon, 5 Feb 2024 at 22:50, Anand Moon wrote: > > > > As per S905 and S905X datasheet add missing cache information to > > the Amlogic GXBB and GXL SoC. > > > > - Each Cortex-A53 core has 32KB of L1 instruction cache available and > > 32KB of L1 data cache available. > > - Along with 512KB Unified L2 cache. > > > > To improve system performance. > > > > Signed-off-by: Anand Moon > > --- > > Datasheet > > [0] https://dn.odroid.com/S905/DataSheet/S905_Public_Datasheet_V1.1.4.pdf > > --- > > As per the Arm Cortex A53 TRM documentation > [0] https://developer.arm.com/documentation/ddi0500/j/Introduction/Implementation-options?lang=en > > Since this SoC supports arm-pmu we could read cache info using perf > [1] https://www.baeldung.com/linux/analyze-cache-misses > > [alarm@archl-librecm ~]$ sudo perf list > > List of pre-defined events (to be used in -e or -M): > > branch-instructions OR branches [Hardware event] > branch-misses [Hardware event] > bus-cycles [Hardware event] > cache-misses [Hardware event] > cache-references [Hardware event] > cpu-cycles OR cycles [Hardware event] > instructions [Hardware event] > alignment-faults [Software event] > bpf-output [Software event] > cgroup-switches [Software event] > context-switches OR cs [Software event] > cpu-clock [Software event] > cpu-migrations OR migrations [Software event] > dummy [Software event] > emulation-faults [Software event] > major-faults [Software event] > minor-faults [Software event] > page-faults OR faults [Software event] > task-clock [Software event] > duration_time [Tool event] > user_time [Tool event] > system_time [Tool event] > > armv8_cortex_a53: > L1-dcache-loads OR armv8_cortex_a53/L1-dcache-loads/ > L1-dcache-load-misses OR armv8_cortex_a53/L1-dcache-load-misses/ > L1-dcache-prefetch-misses OR armv8_cortex_a53/L1-dcache-prefetch-misses/ > L1-icache-loads OR armv8_cortex_a53/L1-icache-loads/ > L1-icache-load-misses OR armv8_cortex_a53/L1-icache-load-misses/ > dTLB-load-misses OR armv8_cortex_a53/dTLB-load-misses/ > iTLB-load-misses OR armv8_cortex_a53/iTLB-load-misses/ > branch-loads OR armv8_cortex_a53/branch-loads/ > branch-load-misses OR armv8_cortex_a53/branch-load-misses/ > node-loads OR armv8_cortex_a53/node-loads/ > node-stores OR armv8_cortex_a53/node-stores/ > br_immed_retired OR armv8_cortex_a53/br_immed_retired/[Kernel PMU event] > br_mis_pred OR armv8_cortex_a53/br_mis_pred/ [Kernel PMU event] > br_pred OR armv8_cortex_a53/br_pred/ [Kernel PMU event] > bus_access OR armv8_cortex_a53/bus_access/ [Kernel PMU event] > bus_cycles OR armv8_cortex_a53/bus_cycles/ [Kernel PMU event] > cid_write_retired OR armv8_cortex_a53/cid_write_retired/[Kernel PMU event] > cpu_cycles OR armv8_cortex_a53/cpu_cycles/ [Kernel PMU event] > exc_return OR armv8_cortex_a53/exc_return/ [Kernel PMU event] > > [alarm@archl-librecm ~]$ perf stat -B -e > cache-references,cache-misses,cycles,instructions,branches,faults,migrations > sleep 5 > > Performance counter stats for 'sleep 5': > > 52794 cache-references:u > 2311 cache-misses:u # 4.38% of > all cache refs > 480343 cycles:u > 140018 instructions:u # 0.29 > insn per cycle > 15012 branches:u > 46 faults:u > 0 migrations:u > > 5.008073381 seconds time elapsed > > 0.000000000 seconds user > 0.006952000 seconds sys > I just wanted to revisit this patch series with some updates on Arm Cortex A53 TRM, here are the L1 and L2 Cache size details. [1] https://developer.arm.com/documentation/ddi0500/j/Level-1-Memory-System/About-the-L1-memory-system?lang=en [2] https://developer.arm.com/documentation/ddi0500/j/Level-2-Memory-System/About-the-L2-memory-system?lang=en [3] https://boardor.com/blog/understanding-the-architecture-of-arm-cortex-a53-cache Thanks -Anand