From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <linux-kernel-owner@vger.kernel.org>
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
        id S1753611AbdECKcy (ORCPT <rfc822;w@1wt.eu>);
        Wed, 3 May 2017 06:32:54 -0400
Received: from mail-wm0-f47.google.com ([74.125.82.47]:38394 "EHLO
        mail-wm0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org
        with ESMTP id S1753372AbdECKcg (ORCPT
        <rfc822;linux-kernel@vger.kernel.org>);
        Wed, 3 May 2017 06:32:36 -0400
MIME-Version: 1.0
In-Reply-To: <20170503094717.GC8233@arm.com>
References: <1493293584-20287-1-git-send-email-gakula@caviumnetworks.com>
 <1493293584-20287-3-git-send-email-gakula@caviumnetworks.com>
 <20170427164237.GA7114@leverpostej> <20170427170030.GF1890@arm.com>
 <CANHdaibvzp22XEa3NnKAKUtrHcWGc9oUcnM8KubcYCzEfOaKJg@mail.gmail.com> <20170503094717.GC8233@arm.com>
From: Geetha Akula <geethasowjanya.akula@gmail.com>
Date: Wed, 3 May 2017 16:02:34 +0530
Message-ID: <CANHdaib0hSFqPmD_WDFTWF6B4OSgFY+popNhK-wiWboTumbBng@mail.gmail.com>
Subject: Re: [PATCH 2/3] iommu/arm-smmu-v3: Add workaround for Cavium
 ThunderX2 erratum #74
To: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
        Geetha sowjanya <gakula@caviumnetworks.com>, robin.murphy@arm.com,
        lorenzo.pieralisi@arm.com, Hanjun Guo <hanjun.guo@linaro.org>,
        sudeep.holla@arm.com, iommu@lists.linux-foundation.org, jcm@redhat.com,
        Linu Cherian <linu.cherian@cavium.com>, linux-kernel@vger.kernel.org,
        linux-acpi@vger.kernel.org, robert.richter@cavium.com,
        catalin.marinas@arm.com, Geetha <gakula@cavium.com>,
        Sunil Goutham <sgoutham@cavium.com>,
        linux-arm-kernel@lists.infradead.org
Content-Type: text/plain; charset=UTF-8
Sender: linux-kernel-owner@vger.kernel.org
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

Hi Will,

We will resubmit the patches based on IORT.


Thank you,
Geetha.

On Wed, May 3, 2017 at 3:17 PM, Will Deacon <will.deacon@arm.com> wrote:
> Hi Geetha,
>
> On Tue, May 02, 2017 at 12:01:15PM +0530, Geetha Akula wrote:
>> SMMU_IIDR register is broken on T99, that the reason we are using MIDR.
>
> Urgh, that's unfortunate. In what way is it broken?
>
>> If using MIDR is not accepted, can we enable errata based on SMMU resource size?
>> some thing like below.
>
> No, you need to get your model number added to IORT after all if the IIDR
> can't uniqely identify the part.
>
> Sorry,
>
> Will