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Mon, 25 Mar 2019 11:17:48 -0700 (PDT) MIME-Version: 1.0 References: <20190325124137.6117-1-zhiyong.tao@mediatek.com> <20190325124137.6117-4-zhiyong.tao@mediatek.com> In-Reply-To: <20190325124137.6117-4-zhiyong.tao@mediatek.com> From: Nicolas Boichat Date: Mon, 25 Mar 2019 11:17:37 -0700 Message-ID: Subject: Re: [PATCH RESEND v3 3/4] arm64: dts: mt8183: add pintcrl device node To: Zhiyong Tao Cc: Rob Herring , Linus Walleij , Mark Rutland , Matthias Brugger , Sean Wang , srv_heupstream , hui.liu@mediatek.com, Eddie Huang , chuanjia.liu@mediatek.com, biao.huang@mediatek.com, hongzhou.yang@mediatek.com, Erin Lo , Sean Wang , devicetree@vger.kernel.org, lkml , linux-arm Mailing List , "moderated list:ARM/Mediatek SoC support" , linux-gpio@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Mar 25, 2019 at 5:41 AM Zhiyong Tao wrote: > > The commit adds pintcrl device node for mt8183 Minor nit: This should say pinctrl (in the commit title as well). > > Signed-off-by: Zhiyong Tao > --- > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 26 +++++++++++++++++++++++++- > 1 file changed, 25 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > index 75c4881bbe5e..cf92504e2a9b 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > @@ -9,7 +9,7 @@ > #include > #include > #include > - > +#include "mt8183-pinfunc.h" > / { > compatible = "mediatek,mt8183"; > interrupt-parent = <&sysirq>; > @@ -197,6 +197,30 @@ > #clock-cells = <1>; > }; > > + pio: pinctrl@10005000 { > + compatible = "mediatek,mt8183-pinctrl"; > + reg = <0 0x10005000 0 0x1000>, > + <0 0x11f20000 0 0x1000>, > + <0 0x11e80000 0 0x1000>, > + <0 0x11e70000 0 0x1000>, > + <0 0x11e90000 0 0x1000>, > + <0 0x11d30000 0 0x1000>, > + <0 0x11d20000 0 0x1000>, > + <0 0x11c50000 0 0x1000>, > + <0 0x11f30000 0 0x1000>, > + <0 0x1000b000 0 0x1000>; > + reg-names = "iocfg0", "iocfg1", "iocfg2", > + "iocfg3", "iocfg4", "iocfg5", > + "iocfg6", "iocfg7", "iocfg8", > + "eint"; > + gpio-controller; > + #gpio-cells = <2>; > + gpio-ranges = <&pio 0 0 192>; > + interrupt-controller; > + interrupts = ; > + #interrupt-cells = <2>; > + }; > + > scpsys: syscon@10006000 { > compatible = "mediatek,mt8183-scpsys", "syscon"; > #power-domain-cells = <1>; > -- > 2.12.5 >