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Thu, 02 Jul 2026 08:53:29 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20260627061723.43014-1-rounakdas2025@gmail.com> <1acf2543-6773-4dad-a94c-76fe3c11ca8a@kernel.org> In-Reply-To: <1acf2543-6773-4dad-a94c-76fe3c11ca8a@kernel.org> From: Rounak Das Date: Thu, 2 Jul 2026 19:53:18 +0400 X-Gm-Features: AVVi8CeYSbQUUYaEQHTr-tGnO-VFWxnr4UkduYfPkq4CsbaMykT6dx7usDNhqFQ Message-ID: Subject: Re: [PATCH v4] EDAC/altera: use ECC manager compatible to select A10/S10 IRQ layout To: Dinh Nguyen Cc: bp@alien8.de, tony.luck@intel.com, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Hi Dinh, Thank you. I am glad that v4 tested clean on both platforms. On the two remaining ifdefs: I originally left them as-is because they guard the double-bit-error path, where the SError handling and arm_smccc_smc() reboot are arm64-specific. Converting to is_s10 would compile s10_edac_dberr_handler() on 32-bit too, but that looks fine since the symbols it needs (arm_smccc_smc, INTEL_SIP_SMC_ECC_DBE, the S10 sysmgr defines) are all available on 32-bit socfpga. I'd like your opinion before sending it. If you'd like them removed, I'll do it as a separate commit, patch 2/2 in a v5 series, since the DB-error path is a distinct change from the IRQ-index selection. Thanks, Rounak